GPSDO question

[PCB.Wiz]

While testing the prototype I discovered something I am unable to explain...

If I leave the Neo-6 timepulse interval set to the default (1 sec interval, 100msec width) and generate the 1uS sampling gate pulses using a monostable, the OCXO tuning voltage measures about 3.2V when the loop is locked.
If I reconfigure the Neo-6 to give a shorter timepulse interval (e.g. 100 msec interval with a 10msec width) then the OCXO tuning voltage drops to around 2V when the loop is locked.
It's still around 2V for shorter intervals and widths such as 10msec interval with a 1msec width, 1msec with a 100uS width or 1msec with a 1uS width.

What happens between 100ms and 1s ?  Maybe graph that ?
It does sound like it’s not locked properly anymore.

[MIS42N]

Any suggestions as to what might be going on?

With the default, the system could be locking on to any frequency divisible by 10. I haven't studied the circuit in detail. The OSC5A2B02 has a specified tuning of 1ppm/V so for a 1V change in the EFC you get a 10Hz change in the output. I'd say the 3.2V locked onto 10.00001MHz.

With a more frequent measurement the problem goes away (10 times a second, frequency divisible by 100 - apart from 10MHz the possibilities are outside the pulling range).

[brian_mk]

Any suggestions as to what might be going on?

With the default, the system could be locking on to any frequency divisible by 10. I haven't studied the circuit in detail. The OSC5A2B02 has a specified tuning of 1ppm/V so for a 1V change in the EFC you get a 10Hz change in the output. I'd say the 3.2V locked onto 10.00001MHz.

With a more frequent measurement the problem goes away (10 times a second, frequency divisible by 100 - apart from 10MHz the possibilities are outside the pulling range).

I think you are right.

I found the OSC5A2B02 datasheet was a bit unclear so I measured the tuning sensitivity myself using a Racal counter.  It gives about 10Hz/Volt which agrees with the 1ppm/V figure you quoted.

Although the frequency counter I am using is not calibrated, it has an internal oven and 0.1Hz resolution. I 'think' it is reasonably accurate once the oven has stabilised.
When the loop is locked with 1PPS and a 3V tuning voltage, the OSC5A2B02 output frequency reads high by around 10Hz.
A tuning voltage of just under 2V gives 10.0000000 MHz on the counter.

So it appears that with a 1PPS timepulse, the loop is locking to 10.00001 MHz as you suggest.
I am trying to figure out a way to prevent this.
I may need to restrict the tuning range so that the loop is unable to pull the OCXO as far as 10Hz - although that may just prevent the loop from locking at all?

In the original article, he used an OCXO with a much lower tuning sensitivity (only 0.66Hz/V).
With a 5V supply than means it can only pull about +/- 1.6Hz max.
He suggests a simple potential divider could be used to reduce the tuning sensitivity (although his concern was the loop transient response rather than locking to the wrong frequency).
The problem with a potential divider is that the op amp that drives the tuning voltage will saturate at around 4V (It has a single 5V supply).
If the voltage is halved giving a tuning sensitivity of 5Hz/V, then it will struggle to reach the 2V required for 10MHz.
Maybe it needs something like a summing amp with variable gain and an adjustable dc offset?

An alternative is to find a solution to the timing pulse reverting back to the 1PPS default when the rechargeable lithium battery voltage drops if the unit is left unpowered for 2 weeks.
This could be the better solution because the loop works a lot faster with less droop when using a shorter pulse interval.

[PCB.Wiz]

So it appears that with a 1PPS timepulse, the loop is locking to 10.00001 MHz as you suggest.
I am trying to figure out a way to prevent this.


In the original article, he used an OCXO with a much lower tuning sensitivity (only 0.66Hz/V).
With a 5V supply than means it can only pull about +/- 1.6Hz max.
Maybe it needs something like a summing amp with variable gain and an adjustable dc offset?

If you are using the circuit in #1, that already has gain and offset.
A (large) resistor across the 66uF  10uF will limit the span away from the 2.500V midpoint.

[brian_mk]

So it appears that with a 1PPS timepulse, the loop is locking to 10.00001 MHz as you suggest.
I am trying to figure out a way to prevent this.


In the original article, he used an OCXO with a much lower tuning sensitivity (only 0.66Hz/V).
With a 5V supply than means it can only pull about +/- 1.6Hz max.
Maybe it needs something like a summing amp with variable gain and an adjustable dc offset?

If you are using the circuit in #1, that already has gain and offset.
A (large) resistor across the 66uF will limit the span away from the 2.500V midpoint.

I think you mean 10uF.

I did wonder about trying something like that.
Ideally the tuning voltage should be 2V at the mid point with a range of just below +/- 1V to restrict the tuning range to just under +/- 10Hz.
My concern is that the loop may just get stuck at the upper or lower end of the range and never lock at all.

Adding a parallel resistor would change what is currently a straightforward integrator into a 'leaky integrator'.
I don't know what 'gain factor' or resistance would be required.
The original design uses worryingly high value (3 x 22Meg = 66Meg) resistors in series feeding into the integrator op amp.

Adding a parallel resistor may upset the loop transient response.
The original designer supplied an LTSpice simulation so I should be able to check what effect it has.

I have been reading up about methods of avoiding false locking in PLLs. Apparently it's a common issue.
It's more of a problem with Type 1 PLLs than Type 2 PLLs such as this one.
One approach might be to monitor the tuning voltage using a window comparator.
If the voltage is outside the window, then inject a small positive or negative current into the integrator (using high value resistors) to bring it in range.
The original design incorporates a 'slew' switch that does a similar thing manually.

[PCB.Wiz]

My concern is that the loop may just get stuck at the upper or lower end of the range and never lock at all.

That will not happen, as if it is not locked, it is phase walking, and the phase comparator will eventually head in the right direction.

I think you mean 10uF. 

Typo fixed.

[MIS42N]

Since I made my previous comment without looking at the circuit in post #1, I thought I'd look at the circuit.

This is completely off topic, but I am so glad I went the microprocessor route. It does everything the circuit does using a microprocessor, 4 resistors, 4 capacitors, 1 LED. It was debugged using nothing more than the serial port and a multimeter.

I think the OSC5A2B02 will need some sort of buffer to feed a signal to the outside world. It is designed to drive HCMOS so not happy feeding into a 50Ω lead. I used an 74HC04. One gate to buffer the OCXO output, feeding another 5 gates (which in hindsight is overkill) to put the signal into the BNC. About 2V peak to peak into 50Ω. The microprocessor clock is bled off through a 22pF cap.

If there's a revised design, use less gates to feed the output (1V p-p should satisfy most requirements) and buffer the 1PPS to another BNC. Or maybe a more stable 1PPS generated by the processor.

[brian_mk]

Since I made my previous comment without looking at the circuit in post #1, I thought I'd look at the circuit.

This is completely off topic, but I am so glad I went the microprocessor route. It does everything the circuit does using a microprocessor, 4 resistors, 4 capacitors, 1 LED. It was debugged using nothing more than the serial port and a multimeter.

I think the OSC5A2B02 will need some sort of buffer to feed a signal to the outside world. It is designed to drive HCMOS so not happy feeding into a 50Ω lead. I used an 74HC04. One gate to buffer the OCXO output, feeding another 5 gates (which in hindsight is overkill) to put the signal into the BNC. About 2V peak to peak into 50Ω. The microprocessor clock is bled off through a 22pF cap.

If there's a revised design, use less gates to feed the output (1V p-p should satisfy most requirements) and buffer the 1PPS to another BNC. Or maybe a more stable 1PPS generated by the processor.

I am using TC4424 drivers to provide 10MHz and 1MHz square wave outputs (together with the timepulse signal) at TTL levels into 50 Ohms.
I also have filtered 10MHz sine wave outputs that can drive 50 Ohms (using discrete transistors).
The sine outputs are isolated using ferrite toroidal transformers to prevent ground loops.
That side of things is not a problem. I just need to sort out the PLL issues...

At the moment I am finding that with a 1PPS timepulse, the loop fails to pull into lock even when the tuning voltage is within 0.5V of the nominal 2V. (i.e. just a few Hz away from 10MHz).
The phase detector output walks from near 0V up to just below 5V as you would expect but the tuning output from the integrator hardly moves.
This is the case even after waiting several minutes.
I have tried reducing the integrator resistor values to speed things up. That makes no difference to the failure to lock.
The problem does not happen if I decrease the timepluse period from 1 sec down to a few hundred millisconds or below.
Perhaps there is insufficient loop gain when the loop only receives a small 1uS pulse once per second?

One thought is that it may be related to the fact I am using CA3130 CMOS op amps instead of the LMC6582 used in the original design.
The CA3130 has an input current of only about 5pA but that is still considerably higher than the 80fA for the LMC6582.
As the integrator uses exceptionally high value resistors, that could make a difference to the loop gain.
I have ordered some LMC6582 devices to test. Unfortunately they are surface mount so I will need to mount them on DIP8 adapters.

[Solder_Junkie]

Brian, I too have a Racal 1998. I also have a Leo Bodnar GPSDO, which is pretty good.

I currently use a dual trace scope for calibration, but fancy a TinyPFA which should make calibration a bit easier.

Mirfield Electronics expects to have stock on the ‘PFA in 3 to 4 weeks. You can also re-flash their VNA to a PFA.

Details of the PFA:
https://www.tinydevices.org/wiki/pmwiki.php?n=TinyPFA.Homepage

SJ

[MIS42N]

I am using TC4424 drivers to provide 10MHz and 1MHz square wave outputs (together with the timepulse signal) at TTL levels into 50 Ohms.

The advantage of knowing your stuff. I used the 74HC04 because I'd seen other circuits using it. It works and the old adage "if it ain't broke..." But the TC4424 looks ideal and would have saved me a bit of board space. And not expensive. Next time gadget, next time.

Sorry I can't help much with the PLL side. The description of the circuit in #1 post did say a FET input op amp. But you may get around it by making the connection between the 74HC74 and the CD4016 a direct connection (why not?) and replacing the 10K resistor between the CD4016 and the op amp (their LMC6582, your CA3130) with 1K. Increase the 100pF capacitor to 2200pF to keep the time constant the same. The 74HC74 is rated to source/sink 5mA and that's the max that will flow through the 1K resistor (and only for 1µs). That will ease the need for a high impedance input, and if you are getting results with 10 PPS then the revision should work for 1PPS.

You'd be able to figure out if this is a workable method by scoping the output of the op amp. If it were working properly, the output should be a fairly flat line for each second (and forget all I said). If leakage is a problem it would drift off one way or other and it would be worth trying the fix.

Messing with the high value resistors may not make much difference - 5pA through 66MΩ is 0.33V which may make the phase lag or lead a bit but not enough to throw the system out. As evidenced by the fact it work with a higher sample rate.

[PCB.Wiz]

At the moment I am finding that with a 1PPS timepulse, the loop fails to pull into lock even when the tuning voltage is within 0.5V of the nominal 2V. (i.e. just a few Hz away from 10MHz).
The phase detector output walks from near 0V up to just below 5V as you would expect but the tuning output from the integrator hardly moves.
This is the case even after waiting several minutes.
I have tried reducing the integrator resistor values to speed things up. That makes no difference to the failure to lock.
The problem does not happen if I decrease the timepluse period from 1 sec down to a few hundred millisconds or below.
Perhaps there is insufficient loop gain when the loop only receives a small 1uS pulse once per second?

Yes, it looks like the filter slew rate, with the very low injection energies of 1us per second, fails to follow that faster phase walk. Looks slow to our eyes, but that is a VERY long time constant filter. 

 If you know when it does start to work, that indicates you are close, and you may be able to tune things.

I did wonder about doubling the injection energy by using a XOR gate + delay RC to give a pulse on each edge, but even that still has 900ms hold-over.

The fact the original design has a manual helper ‘slew’ 3 way paddle switch, suggest manual assist could be part of normal operation. 

[brian_mk]

I was thinking about the problem early this morning while still in bed. 
I came up with what seems like a plausable explanation...

When the two frequencies differ, the phase detector outputs a sawtooth waveform that represents the phase difference.
In the idealised case, the sawtooth goes from 0V to 5V and is centered around 2.5v.
At the 0V and 5V points, where the sawtooth jumps, the phase difference between the two signals reaches 2 * PI.
When the sampling interval is long (i.e. once per second) the sawtooth is not linear but changes in sudden steps.
When you integrate the sawtooth over a long period, the integrator output (=OCXO tuning input) remains at the midpoint i.e. 2.5V and the loop fails to lock.

It will only lock if the sawtooth does not jump (i.e. the phase difference does not cross the 2 * PI threshold) before the output from the integrator has had time to respond to the ramp.
The nonlinear sawtooth resulting from the long sampling interval must make this situation worse.
It means the loop has a small capture range; the two frequencies have to be close to begin with.

[MIS42N]

I too have been thinking about that circuit. I did some calculations to see if my assumption that op amp leakage is a problem. Turns out it isn't.

There is a pulse 1µs wide taking current from Q1 of the 74HC74 through 20kΩ to charge/discharge the 100pF capacitor input to pin 3 of the LM6582.
The maximum voltage possible across the 20kΩ is 5V. So the maximum current possible is 5/20,000 = 250µA. For 1µs.
That's equivalent to 250pA continuous into 100pF which should result in a 'jog' of more than 1V at worst case. Using an op amp with leakage of 5pA should be fine and the circuit should work.

The write up says "A tuning sensitivity anywhere near this value will work fine, from as high as 1 x 10-7 per volt ...". The problem is the tuning sensitivity is much higher at 1 x 10^-6 per volt.

I think the solution is to add an extra divide. There's nothing sacred about divide by 10. An extra divide by 2 inserted between the 74HC190 and the 74HC74 may be enough and divide by 4 almost certainly (hedging my bets here, I think 100% but nothing is guaranteed until it committed to hardware). The 1MHz output can still come from the output of the 74HC190.

With an extra divide by 4, the total is divide by 40 so the system can only lock onto frequencies divisible by 40. That takes it well out of the pulling range so can only lock onto 10MHz. It also means the frequency window (the time for the PLL to lock onto the signal) is 4 times longer. The pulse width will be longer at 4µs so 4 times as much charge goes into the capacitor input to pin 3 of the op amp. Which makes any leakage problem is less important. To retain the time constant it should be increased to 470pF and the timing of the 74HC74 monostable needs increasing to 4µs.

Thoughts?

[PCB.Wiz]

With an extra divide by 4, the total is divide by 40 so the system can only lock onto frequencies divisible by 40. That takes it well out of the pulling range so can only lock onto 10MHz. It also means the frequency window (the time for the PLL to lock onto the signal) is 4 times longer. The pulse width will be longer at 4µs so 4 times as much charge goes into the capacitor input to pin 3 of the op amp. Which makes any leakage problem is less important. To retain the time constant it should be increased to 470pF and the timing of the 74HC74 monostable needs increasing to 4µs.

Moving away from lock-alias points seems a good idea, and you can use any division.
Suitable single-package choices could be HC393, HC4520, or even a HC4060 which can AC couple to 10MHz in, but has /16 as smallest tap.
HC390 is dual decade, for other non-binary divide options.
Binary is ok for divides up to /128 - you just need to ensure you have exact N cycles per pps (or faster set) frame. so eg 1250 is a ok faster pps rate for moderate binary dividers.

[brian_mk]

Update...

The false locking problem no longer happens.
The reason is that in my version of the circuit, the OCXO is fed from a separate 5V regulator. It includes a current sensor that detects when the OCXO reaches temperature.
Until the OXCO has warmed up, the loop remains open and tuning voltage is derived from a preset trimmer.
When the current sensor detects that the OCXO has reached temperature, a relay switches the tuning voltage to the loop integrator output.
Previously I set the preset tuning voltage to about 3V. This resulted in the false locking problem.
It was only after I tried increasing the Neo-6 timepluse interval above 1PPS I realised that the correct tuning voltage should be about 2V.
Having corrected this, the loop no longer erroneously locks to 10,000,010 Hz at startup.

The LMC6852 low input current dual op amps I ordered arrived. I mounted one on a DIP8 adapter and connected it in place of the two CA3130 devices.
As expected it reduces the droop over the 1 second sampling interval. Otherwise it makes little difference.

I am left with one problem; the acquisition range of the loop...

From my observations, the loop is unable to lock when it is cycle slipping (i.e. the phase detector is crossing the 2 * PI threshold).
I can get this to happen by jogging the center-off slew switch so that the tuning voltage is above or below 2V by a couple of hundred millivolts.
In this state the phase detector is outputting a 1V->3V sawtooth waveform. It no longer provides a voltage proportional to the phase error.
(The sawtooth is not linear but changes in steps when the 1PPS samples occur - although I don't think that this affects this issue).
The integrator output is the average of the 1V->3V sawtooth and remains steady, somewhere near the middle; it does not pull the OCXO into lock.
Unlike some other types of phase detector, there appears to be no offset that gradually pulls the OCXO towards the required frequency when cycle slipping is taking place.

I managed to download PDF copies of a couple of PLL books: Phase Lock Basics (Egan) and Phase Lock Techniques (Gardner).
Both books are full of lots of useful information including different types of PLL, loop filters, transient response etc.
They discuss various 'Lock Assist' techniques that help the loop to acquire initial lock.
This includes adding a slow sweep to the tuning signal, including a frequency discriminator in addition to a phase detector, open loop frequency acquisition etc.
The 'open loop frequency acquisition' technique gave me an idea...

My version of the circuit includes a window comparator that monitors the output from the integrator.
It is used to light an LED when the tuning voltage is within about +/- 100mV of the 2V needed for 10,000,000 Hz.
What if I use the window comparator to switch the startup relay and connect the OCXO tuning voltage to the preset trimmer whenever the integrator output is outside the lock range? i.e. open the loop in a similar way to what happens at startup.
When I tried it, I found that the system can still get stuck in a state where, although the open loop preset tuning voltage is close to the required 2V, the phase detector output is cycle slipping and the integrator output remains stuck outside the lock range indicated by the window comparator.

I am still searching for a solution.

[MIS42N]

The LMC6852 low input current dual op amps I ordered arrived. I mounted one on a DIP8 adapter and connected it in place of the two CA3130 devices.
As expected it reduces the droop over the 1 second sampling interval. Otherwise it makes little difference.

So my analysis was right! Your op amps were adequate.

I am still searching for a solution.

Have you dismissed the extra divide by 4 option?

[PCB.Wiz]

Did you find out what sample rate does lock ok ? Iirc it was some hundreds ms, so you are close ?
 As the sample rate changes, the LPF also changes slew rate, so a value tweak may be all you need.

[brian_mk]

I think I may have found a solution...

After I realised that this type of phase detector will only work correctly when not cycle slipping, I decided to automatically steer the OCXO tuning voltage when the loop is out of lock by injecting a positive or negative slew current into the integrator.
I re-configured the window comparator that monitors the integrator output as two separate comparators giving two logic signals.
One indicates the tuning voltage is above the high cycle slipping threshold, the other indicates it is below the low threshold.
These signals control a pair of analogue switches that switch a high value resistor to inject either a positive or negative current into the integrator and correct the error.
The thresholds are set just inside the tuning voltages where cycle slipping begins.
Rather than use 0v and 5v to supply the current, I am using the potential divider that provides the reference voltages for the comparators.

After modifying the prototype, it appears to work as expected.
It still needs more testing but it's looking hopeful (fingers crossed).
I'm glad I went to the trouble of building a hand wired prototype before making a PCB.

[brian_mk]

A couple of pics of the finished project.

It's taken longer than expected.
It may look a bit old-school but I still prefer using through hole components for home constructed test equipment.
I used a 20 segment bar graph istead of an analogue meter - it was easier to fit in the case.
I am currently in the process of using the GPSDO to calibrate several items of test gear.
So far it seems to be working well.
I used a radio tuned to BBC R4 198kHz along with a signal generator with it's EXT 10 MHz input connected to the GPSDO for a quick accuracy test.