GPSDO question

[brian_mk]

I bought a used Racal 1998 counter (eBay of course).
It has the OCXO option. I'd like to check/calibrate it.

I am a retired engineer / hobbyist with a very limited budget.
The counter has 9 digits, so it would be nice to check if the least sig digit is accurate.
For example: 10,000,000.0 Hz to within +/- 0.1Hz. i.e about 1 in 10^8.
Is that too ambitious?

Naturally I started investigating GPSDOs.
I could buy a Chinese one on eBay for about £150.
Then I thought it might be an interesting project to try and construct something.

There are a lot of designs and ideas on the internet.
Some are more than I need / too complex / too expensive / too time consuming.
I am not a time nut looking for ultimate precision.
I don't really want to spend a lot of time / effort / expense with complex designs involving uPs & software.

I have a GPS receiver with a Neo-6M salvaged from a crashed drone I found in a hedge :-)
It still works and produces a 1PPM signal, so I figure I should be able to make use of it.

I found this easy to understand semi-digital/semi-analogue design:-

http://techlib.com/electronics/GPSstandard.htm

My questions to the experts...
"Would this design meet my requirements?"
"Are there any obvious limitations / problems I should be aware of?"

One concern is the analogue loop filter that uses a 66M Ohm resistor. Surely not good in humid conditions?

[Gyro]

10^8 isn't unrealistic. It's a bit close to bed time to go into detail, but irrc, with a USB serial adaptor and the appropriate S/W from the u-blox site, it's possible to set the timepulse output to anywhere between 0.25Hz and 10MHz.

It won't be as stable as a full GPSDO, but should be sufficient for your accuracy needs. Note that any frequency that isn't a sub-multople for the internal 64MHz module clock will have jitter, so it is best set to 8MHz output. In practice though, I have found that the gate time of the frequency counter is sufficient to give a stable reading at 10MHz too.

[PCB.Wiz]

I bought a used Racal 1998 counter (eBay of course).
It has the OCXO option. I'd like to check/calibrate it.

I am a retired engineer / hobbyist with a very limited budget.
The counter has 9 digits, so it would be nice to check if the least sig digit is accurate.

A quick, simple check should be to simply measure the 1pps, any decent counter should be able to report that to 8-9 digits as Frequency and Period.

As mentioned above, if you have the right GPS module, you can redefine the GPS 1pps with the right connection and SW, and it will give you an averaged correct value up to MHz.
10MHz has some jitter from the 48MHz? GPS locked clock, but you will get exactly 5 cycles in 500ns, derived from exactly 24 cycles.
I find this

The u-blox devices have a feature that makes a reference frequency (derived from its internal 48 MHz clock) directly available, rather than just the 1 pps signal that is not all that easy to use for locking a 10 MHz reference to it. The u-blox signal, which can provide a jittery 10 MHz, or, preferably, integer-divided 48 MHz (e.g., 8 or 4 or 2 MHz),

A PLL can average that, and I saw one design where a user applied a 10MHz crystal as a very high Q ringing filter, which makes scope checks easier.

There is also a lot here...
https://www.eevblog.com/forum/projects/yet-another-diy-gpsdo-yes-another-one/

and this approach throws different hardware at the problem, using a 10Mhz divider and leaving the 1pps untouched.
https://www.edn.com/simple-gps-disciplined-10mhz-reference-uses-dual-pwms/
The Author uses an external 74LV8154 32b counter, that needs many pins connected, but it does manage the 10MHz division externally to the MCU
 

[brian_mk]

10^8 isn't unrealistic. It's a bit close to bed time to go into detail, but irrc, with a USB serial adaptor and the appropriate S/W from the u-blox site, it's possible to set the timepulse output to anywhere between 0.25Hz and 10MHz.

It won't be as stable as a full GPSDO, but should be sufficient for your accuracy needs. Note that any frequency that isn't a sub-multople for the internal 64MHz module clock will have jitter, so it is best set to 8MHz output. In practice though, I have found that the gate time of the frequency counter is sufficient to give a stable reading at 10MHz too.

Unfortunately the Neo-6M that I have only allows the Timepulse to be configured between 0.25Hz and 1kHz. The Neo-6T allows it to be set up to 10MHz.
That means either using a phase detector at the default 1PPS or configuring the Timepulse output to 800Hz.
If the Neo-6M uses a 48MHz clock, 800Hz is the highest frequency that is an integer sub multiple for optimum jitter performance.

Strangely though, the link below indicates the Neo-6M uses a 26MHz crystal?
https://portal.u-blox.com/s/question/0D52p00008HKDu7CAH/find-frequency-at-which-ublox-neo6m-is-working-at

Anyway, the design in the link I gave in my original post uses the default 100ms wide 1PPS output.
It generates a 1uS wide pulse from the 1PPS signal using a monostable. The 1us pulse is used to sample a 1MHz signal obtained by dividing the 10MHz OCXO by ten.
The result is a voltage proportional to the phase difference between the OCXO and the 1PPS.
This voltage is fed through an analogue active filter with a long time constant to the OCXO tuning control.
It seems quite a neat and simple idea.
I am wondering what the limitations might be.

BTW I already have some of the cheap, ex-equipment Chinese CTI OSC5A2B02 10MHz OCXOs.
They use a 5V supply, 0->4V control voltage and output a square wave with 74HC logic levels.
I think they would fit in well with the design above.

[Gyro]

I bought a used Racal 1998 counter (eBay of course).
It has the OCXO option. I'd like to check/calibrate it.

I am a retired engineer / hobbyist with a very limited budget.
The counter has 9 digits, so it would be nice to check if the least sig digit is accurate.
For example: 10,000,000.0 Hz to within +/- 0.1Hz. i.e about 1 in 10^8.
Is that too ambitious?

Naturally I started investigating GPSDOs.
I could buy a Chinese one on eBay for about £150.
Then I thought it might be an interesting project to try and construct something.

There are a lot of designs and ideas on the internet.
Some are more than I need / too complex / too expensive / too time consuming.
I am not a time nut looking for ultimate precision.
I don't really want to spend a lot of time / effort / expense with complex designs involving uPs & software.

I have a GPS receiver with a Neo-6M salvaged from a crashed drone I found in a hedge :-)
It still works and produces a 1PPM signal, so I figure I should be able to make use of it.

I found this easy to understand semi-digital/semi-analogue design:-

...

Now that I'm awake... I understand your desire not to get into uPs etc, even if they may lead to an overall more compact or long term stable design with holdover etc.

Also being a retired engineer with limited budget, I put together a really simple GPSDO breadboard design using a basic PLL, a cheap OCXO, and an LEA-6T. These specific 6T boards were being sold really cheaply on ebay at the time for drone use (which I never did understand). The LEA-6T is specifically designed for timing purposes, slightly different firmware, two timepulse outputs rather than just the one, and, (I think) a 64MHz TCXO rather than VCXO. As I mentioned in my previous post, I was able to calibrate my counter (a Philips PM6622) with stable results just using one of the timepulse outputs of the module. My motivation for the GPSDO was really to get a nice stable jitter-free 10MHz output, and just for the hell of it. It's still a breadboard, but I do intend to finisjh it some day.

I started two threads, one on the LEA-6T board, which will probably be at least of some use for the LEA-6M too, and a second thread detailing my PLL based GPSDO breadboard. The PC based configuration software that I used was u-center, available from the u-blox website.

https://www.eevblog.com/forum/projects/ebay-u-blox-lea-6t-gps-module-teardown-and-initial-test/

https://www.eevblog.com/forum/projects/my-u-blox-lea-6t-based-gpsdo-(very-scruffy-initial-breadboard-stage)/

As far as I could establish, the GPSDO was achieving probable a couple of orders of magnitude better than the 1e-8 that you are looking for. I'm not really a metrologist either, I just wanted something 'good enough' and simple to tinker with.


If you're looking for something ready made, I also suggest one of Leo Bodnar's (forum member). Programmable frequency GPSDO units... https://www.leobodnar.com/shop/. He's also in the UK.


EDIT: I've just seen your above post. It's a shame the timepulse on the 6M can't be set higher. I think you would be ok with 1kHz (the high divide ratio, compared to 10MHz, would eliminate jitter). Obviously you would need a higher divide ratio from the OCXO and to play with the PLL filter.

I know it's uP in the general sense, but you may want to look at a picDIV for the divider (PD4 would fit the bill)... http://www.leapsecond.com/pic/picdiv.htm. Otherwise, a (preferably synchronous) divider chain.

[WatchfulEye]

If you set the time pulse frequency of the GPS receiver to something in the measurement range of the counter (eg. 100 Hz) and use a gate time of 20 seconds, then that should be sufficient to achieve 1e-8 accuracy. No additional hardware needed.

GPS receivers have quite a lot of jitter in the time pulse due to the internal clock, and also GPS solution errors. A gate time sufficient to average this out is a good idea.

[Gyro]

If you set the time pulse frequency of the GPS receiver to something in the measurement range of the counter (eg. 100 Hz) and use a gate time of 20 seconds, then that should be sufficient to achieve 1e-8 accuracy. No additional hardware needed.

GPS receivers have quite a lot of jitter in the time pulse due to the internal clock, and also GPS solution errors. A gate time sufficient to average this out is a good idea.

Agreed. Calibrating to that sort of accuracy isn't the demanding requirement that it once was. GPS changed everything in terms of frequency reference traceablility. Pick a USB-Serial adapter that has the appropriate selectable output voltage and you can power the module from USB too.

[S57UUU]

If your GPS can output 1kHz, it should be easy to make a simple PLL for a 10MHz crystal. For example, 2X 74HC390 + 74HC4046. Such an analog loop will be too fast to be a "flywheel", and will track all of the GPS errors, but 8 digits should be easy and 9 may be achievable.

[PCB.Wiz]

Unfortunately the Neo-6M that I have only allows the Timepulse to be configured between 0.25Hz and 1kHz. The Neo-6T allows it to be set up to 10MHz.
That means either using a phase detector at the default 1PPS or configuring the Timepulse output to 800Hz.
If the Neo-6M uses a 48MHz clock, 800Hz is the highest frequency that is an integer sub multiple for optimum jitter performance.

1000Hz is still an integer divider ?  /60000 0r /48000 ?

Strangely though, the link below indicates the Neo-6M uses a 26MHz crystal?
https://portal.u-blox.com/s/question/0D52p00008HKDu7CAH/find-frequency-at-which-ublox-neo6m-is-working-at

Yes, that is then locked again inside their MCU.
I did see one design where they took the trouble to lock that 26MHz, which must reduce the additional corrections needed, but that involved hacking into the GPS module.

Anyway, the design in the link I gave in my original post uses the default 100ms wide 1PPS output.
It generates a 1uS wide pulse from the 1PPS signal using a monostable. The 1us pulse is used to sample a 1MHz signal obtained by dividing the 10MHz OCXO by ten.
The result is a voltage proportional to the phase difference between the OCXO and the 1PPS.
This voltage is fed through an analogue active filter with a long time constant to the OCXO tuning control.
It seems quite a neat and simple idea.
I am wondering what the limitations might be.

It is neat and simple, the main limitation is the 'long time constant' needs to be very long for a 1us impulse every second, so the testing and parts are less friendly.
If you have 1us sample windows and 1s waits, a that's 1M:1 leakage/noise to information ration.
Even 1kHz helps improve that to 1000:1
You may want to seek a low leakage analog switch for the PLL aperture sampler.
Addit: nailing down leakage does not seem easy, It is highly temperature dependent and they only worry about logic-level testers.
I did find this
https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/854115/sn74lvc1g3157-input-leakage-current
and this seems to define low leakage
https://datasheet.lcsc.com/lcsc/1912111437_DIOO-DIO3157ESC6_C444615.pdf
and this DIO3166 is single channel 
https://www.dioo.com/diooAdmin/api/upload/img/1679364769894.pdf

I wonder if the older 15V CMOS is lower leakage ? I did find a SOT25 version of a single gate CD4066 : ROHM BU4S66G2 and Toshiba TC4S66F

Their /10 design to 1MHz could also help you compare two GPS, one with a 10MHz setting and one with 1pps, as /5 or above removes the 48M:10M edge placement jitter.

BTW I already have some of the cheap, ex-equipment Chinese CTI OSC5A2B02 10MHz OCXOs.
They use a 5V supply, 0->4V control voltage and output a square wave with 74HC logic levels.
I think they would fit in well with the design above.

Yes.

[MIS42N]

For 1 part in 10^8 the GPS module (Neo-6M) output is fine, no GPSDO required. Just make a few measurements and average. If this is an infrequent calibration then it is not worth going down the GPSDO route.

A problem with most GPSDOs is it is difficult to know how accurate they are. If the GPS module is relying on minimal signal its output can instantaneously wander quite a bit. Phase locked loop designs may follow this faithfully or average fluctuations out. It is a compromise between getting a quick lock and getting a stable output. If the GPSDO gives access to the NMEA messages from the GPS module then at least the quality of the GPS signal can be determined and infer the GPSDO is accurate. An accuracy better than 1 part in 10^9 is usual but not guaranteed.

I produced a basic microprocessor based design a few years ago https://www.eevblog.com/forum/projects/budget-gpsdo-a-work-in-progress/ the first version running from a 5V wall wart used two ICs (PIC16F1455 and 74HC04) and an OSC5A2B02 OCXO. It is self checking so it indicates if it is running within specification (1 part in 10^9) so gives some confidence when using the output. Although microprocessor designs involve software they can be much more informative than other designs and reduce the component count. Excluding the wall wart (which could be a surplus phone charger) and the GPS module the parts are about $20AU (less in $US).

With some modification the same design wrapped in better power supplies and good GPS signals has proven to be good for accuracy of 4 parts in 10^11 (as measured by its self check feature). I have been thinking of some modifications to the PCB to drive this down further (some poor design on my part).

[brian_mk]

It is neat and simple, the main limitation is the 'long time constant' needs to be very long for a 1us impulse every second, so the testing and parts are less friendly.
If you have 1us sample windows and 1s waits, a that's 1M:1 leakage/noise to information ration.
Even 1kHz helps improve that to 1000:1
You may want to seek a low leakage analog switch for the PLL aperture sampler.
Addit: nailing down leakage does not seem easy, It is highly temperature dependent and they only worry about logic-level testers.
I did find this
https://e2e.ti.com/support/switches-multiplexers-group/switches-multiplexers/f/switches-multiplexers-forum/854115/sn74lvc1g3157-input-leakage-current
and this seems to define low leakage
https://datasheet.lcsc.com/lcsc/1912111437_DIOO-DIO3157ESC6_C444615.pdf
and this DIO3166 is single channel 
https://www.dioo.com/diooAdmin/api/upload/img/1679364769894.pdf

I wonder if the older 15V CMOS is lower leakage ? I did find a SOT25 version of a single gate CD4066 : ROHM BU4S66G2 and Toshiba TC4S66F

Agreed - leakage was one of my concerns - both in the sampling gate and in the analogue filter.

To get a long time constant, the filter uses a 66Meg resistor (actually 3x 33Meg). It would only need a small amount of moisture/dirt to throw it way out.
The PCB would need slots and guard rings to try and minimise the effects.

It did occur to me that if the Timepulse were changed from 1PPS to 1kHz, the design should still work without any changes.
It would mean that the 1MHz signal is sampled once per millisecond rather than once per second. That would greatly reduce the effect of leakage in the sampling gate.
In this case though, does the design offer any advantage over a standard 'exclusive OR' phase detector?

BTW: The analogue filter circuit used is unusual.
The text describes it as a 'third order filter' but it looks different to any third order LPF single op amp designs that I have seen.
I have been unable to find information on how to calculate the R & C component values for a given cut off frequency.
I tried simulating it in LTSpice but the results look rather odd.

[S57UUU]

Yes, 26000000 Hz / 1000Hz = 26000, so it will be a nice symmetric square wave.

[PCB.Wiz]

It did occur to me that if the Timepulse were changed from 1PPS to 1kHz, the design should still work without any changes.
It would mean that the 1MHz signal is sampled once per millisecond rather than once per second. That would greatly reduce the effect of leakage in the sampling gate.
In this case though, does the design offer any advantage over a standard 'exclusive OR' phase detector?

The xor needs 50% duty cycle and equal frequencies on each pin.
I'd choose a 7474 with schmitt pins.

BTW: The analogue filter circuit used is unusual.
The text describes it as a 'third order filter' but it looks different to any third order LPF single op amp designs that I have seen.
I have been unable to find information on how to calculate the R & C component values for a given cut off frequency.
I tried simulating it in LTSpice but the results look rather odd.

I'd call it second order, with differing corners.
The first LPF is 10k+10k+100p, which appears fast, but that is sampled 1:1M, so actually has a time constant of ~2s, the second stage has time constant of ~31s
 
With the faster update PFD frequency, you could speed up those filters a little, but a long filter time does help to average things.

[brian_mk]

Does anyone know what happens to the pulse width of the Neo-6M Timepulse signal if the frequency is re-configured?
At the default 1PPS, the pulse width is 100ms.
I am guessing that the pulse width is fixed for very low frequencies but changes to a 1:1 mark space ratio square wave above 10Hz?

Edit: I just discovered this post from "Johnny B Good" in another thread...
https://www.eevblog.com/forum/metrology/what-do-you-want-from-a-gpsdo/100/

====

"I mention this on account this new found interest in test and measurement kit has set me off on a seemingly never ending quest for better and more accurate gear, aka a GPSDO I can rely on and be proud of. Lately, in earlier postings here, I've been bemoaning my problems with getting a 5 volt 13MHz OCXO to phase lock against my cheap NEO-6M's 1kHz PPS (it's a make do for now substitute for the original M8N module I damaged with an injection of 12 volts into its PPS line a couple of weeks back).

 All this time I'd been blaming first the XOR gate phase detector circuit and then the 4046 phase detectors for not doing 'their job' and, only now between this and the previous post, discovered a rather strange fact about the PPS signal from a NEO-6M (or at least this NEO-6M) when it's programmed to output a 1ms second pulse with a 50% duty cycle (1KHz sq wave).

 Up until just prior to this post, I'd only ever quickly checked out the PPS and divider chain  1KHz output waveforms, preferring to monitor the 13MHz OCXO and FY6600 outputs when testing my crude PLL setup. It's only since I decided to take a much closer look in detail at the 1KHz signals going into the 4046's phase detectors, whilst monitoring the output voltage, that I've finally discovered the root cause of my crudely lashed up on prototyping bread board GPSDO test setup's failure to lock onto the GPS reference. It turns out to have been all to do with the NEO-6M's strange habit of slowly  wittling away at the positive going pulse, shrinking its width until it disappears up its own backside to instantly reincarnate itself as a full fat sq wave, remaining so for the following five or so minutes before starting another cycle of shrinkage over the next 5 or so minutes.

 If it hadn't been for the fact that I'd upgraded the FY6600 to an OCXO clock, I doubt I'd have been able to hand adjust the tuning pot on the OCXO to keep it close enough to the leading edge of the 1KHz PPS pulse to observe such weirdness (I'm not sure the original 0.1ppm 50MHz TCXO upgrade would have been enough of an improvement to have pulled off such a stunt).

 It's no wonder the XOR gate failed to produce any meaningful failure behaviour let alone actually function as intended other than for relatively brief moments when it seemed to be locking in an offset fashion. The type 2 phase detector in the 4046 should have gotten round the non-square waveform issue but I'm guessing it was triggering on the trailing falling edge which would have been slowly happening at earlier and earlier times in the cycle for half of this 10 or so minute cycle before jumping back to a sq waveform for another 5 or so minute round of fun and games. No wonder it was slowly driving me round the bend these past few evenings (including midnight to 5 or 6 in the am if truth be known  ).

 Anyway, that's just a taster of the sort of process that sucks you ever deeper into the mad mad world of DIY test gear and electronic projects in general. BTW, I think, now I've got the use of the type 2 phase detector in that 4046 which doesn't rely on the waves being square, I'll have a go at reprogramming the NEO-6M to generate the narrowest pulse possible (10 microsecond, afaicr) and see how it behaves at that setting.
"
====

It indicates the pulse width of the Timepulse is separately configurable to the frequency (as low as 10uS miniumum).
However, from the report above, I am a concerned about how the mark-space ratio varies over time.

[brian_mk]

Today I tried changing the Timepulse config to give 1kHz with a 1uS pulse width. That worked as expected.

However the change doesn't appear to be saved in non-volatile memory even though I configured u-center CFG to save in BBR and FLASH

The receiver board has a button cell that measures 1.8V and is connected to the Neo V_BCKP pin.
The datasheet suggests that 1.8V should be sufficient to maintain the on-chip battery backed RAM.

Am I missing something?

Edit:
My bad. I don't think I understood the u_center interface.
I assumed that if the CFG setting includes 'BBR' it would automatically cause ALL future parameter changes to be saved in battery backed RAM.
It appears you have to 'Send' the CFG setup AFTER changing a bunch of parameters in order to save them.
After I did that, the Timepulse change remains after power cycling the device.

Being able to set the Timepulse width to 1uS means that the monostable used to generate the sampling pulse for the 1MHz signal will not be needed.

[PCB.Wiz]

Today I tried changing the Timepulse config to give 1kHz with a 1uS pulse width. That worked as expected.
... After I did that, the Timepulse change remains after power cycling the device.
Being able to set the Timepulse width to 100uS means that the monostable used to generate the sampling pulse for the 1MHz signal will not be needed.

I think you meant 1.00us?
Yes, that's a great setting idea for that specific circuit.    (but it may not be fully GPS unit portable ?)
You could scope the phase detector to check for strange wanderings, like those reported. Maybe try heating/cooling, in case it's some correction artifact.

[brian_mk]

Sorry I meant 1uS. I've edited and corrected the error.

[brian_mk]

An update on the GPSDO project.

I decided to construct a hand wired prototype before making a pcb. It took some time to build but it gave me a chance to check and try a few things.
It's now basically working.

I found that at least two of the five used OCXOs I bought require a tuning voltage of just over 3V to lock.
I think they should be about 2V when new. I guess they have drifted with age. Not a real issue.

One of the CMOS op amps I intended to use as a high impedance buffer in the sample and hold oscillated at HF for some unnown reason. I had to replace it with an alternative part.

A bigger problem is that I found the small 3V rechargeable lithium cell on the Neo-6M module only lasts for a couple of weeks when not powered.
It powers the Battery Backed Ram which contains clock data, latest position data and module configuration.
I reconfigured the device to change the 1PPS timepulse to 1kHz. However when the battery voltage drops, the signal reverts back to 1PPS.

The phase detector design can operate with a 1PPS signal but it means the loop filter needs a long time constant.
It would be better if I could find a way to maintain the 1kHz setting.
I have read that some people use a uP to configure the device over the serial link every time it powers up. That solution seems a bit over the top.
I was wondering about replacing the button cell with a higher capacity rechargeable lithium battery that would last a few months.

[MIS42N]

Sorry I meant 1uS. I've edited and corrected the error.

You really mean 1µs - capital S stands for the SI unit siemens. The s for seconds is lower case.
I didn't know this until pointed out to me.
Capital letter units are named after people - https://en.wikipedia.org/wiki/List_of_scientists_whose_names_are_used_as_units
All the rest are small except the litre (international spelling) or liter (American English spelling) which can be L or l (I do not know why).
Along the same lines, quantities a million or more are capitals, less are small. So k = kilo M = mega. This allows distinguishing mΩ from MΩ (milliohm and megohm).
Very pedantic.

[MIS42N]

An update on the GPSDO project.

I think you are hooked.
You said "I don't really want to spend a lot of time / effort / expense with complex designs involving uPs & software." but are well into spending a lot of time avoiding a µP.
This is a quote from someone who built my GPSDO.

I'm pleased to say that this device works exactly as intended. I had a few hiccups along the way, mainly with supply of recycled NEO-6M devices from Aliexpress (poor soldering/shorted chips, shorted voltage regulators...you name it).

Apart from that, the device works very well. It is sitting, stable, on my desktop. It does lose calibration a few times a day (been running 48 hours) but quickly regains it with the inbuilt algorithm. It also seems sensitive to the activation of other test devices (esp clock-driven) on the bench, so could do with some sort of shielding.

Overall: excellent project. The fact that this is working for the price is mind-boggling. I feel this thread needs some traction.

That was the first version. It cost about $20AU minus GPS unit. I addressed the sensitivity issue in the second version. I sold some kits for the second version (including the GPS unit and active antenna but not a case or 12V supply) for $45AU - about £25
It does not require a modification to the GPS unit. It is self calibrating (you build it, you run it for a few hours. Nothing to tune). It tells you on an LED if it is running out of spec (1 part in 10^9 or 0.01Hz) - something that you won't find in any other GPSDO at that price.
Are you sure it's worth avoiding the µP solution?
P.S. I sold all the version 2 kits and don't intend to create any more. The design is published in Silicon Chip magazine May 2023.

[brian_mk]

The project was partly an exercise to keep myself busy since retiring. It's just a hobby.
There is only so much mindless daytime TV you can watch before you turn into a brain dead zombie.

It's taken longer and cost more than I expected. I could probably have bought a ready built Chinese GPSDO more cheaply but where's the fun in that?

I worked as an embedded software engineer for many years, so although I could do it, I'm no longer that keen on spending my time writing code these days.

As for the 's' or 'S', my eyesight is now so bad I have trouble both reading and typing. I make so many embarassing typos these days.

[MIS42N]

The project was partly an exercise to keep myself busy since retiring. It's just a hobby.
There is only so much mindless daytime TV you can watch before you turn into a brain dead zombie.

It's taken longer and cost more than I expected. I could probably have bought a ready built Chinese GPSDO more cheaply but where's the fun in that?

I worked as an embedded software engineer for many years, so although I could do it, I'm no longer that keen on spending my time writing code these days.

As for the 's' or 'S', my eyesight is now so bad I have trouble both reading and typing. I make so many embarassing typos these days.

As I thought - hooked.

I had no need of a GPSDO, just seemed an interesting challenge. Kept me away from that mindless daytime TV for a few years. Now I'm looking for the next challenge (which I think is house renovation - for something completely different).

I was, and still am, keen to write assembler software. The PIC processor at the heart of the GPSDO uses all 3 timers, a comparator, interrupt on change, and its UART. It handles between 40,000 and 50,000 interrupts a second from many (I think 9, I'd have to look at the code) sources. The aim was to replace components with software. The clock for the processor comes from the 10MHz OCXO, and the 1pps from the GPS module goes direct to the processor also. No external  phase detector. The control voltage for the OCXO is highly filtered dithered PWM (which accounts for 40,000 interrupts) for microvolt control, so no DAC.

And of course using a processor allows lots of extras - self checking, status LED, user interface (optional) to monitor in detail what happens, a limited (up to a couple of hours) history facility, more. And all that for less than $5 (about £3?). Hard to go past.

[brian_mk]

If I went down the uP path,  would have used an ESP32. It has a DAC and you can use the WiFi to create an all singing, all-dancing web based user interface for a smartphone. 

I discovered why the CMOS op amp in the sample & hold & loop filter was oscillating. I used an old CA3130 from my junk box. It needed an added frequency compensation cap. The CA3130 has the advantage of an extremely high input impedance.

When running with a 1PPS timepulse, the sample & hold droops by about 50mV between sampling periods. I guess this is down to the non-infinite input impedance of the op amp buffer. It relies on the loop filter to remove the phase jitter that would otherwide cause.

[brian_mk]

While testing the prototype I discovered something I am unable to explain...

If I leave the Neo-6 timepulse interval set to the default (1 sec interval, 100msec width) and generate the 1uS sampling gate pulses using a monostable, the OCXO tuning voltage measures about 3.2V when the loop is locked.
If I reconfigure the Neo-6 to give a shorter timepulse interval (e.g. 100 msec interval with a 10msec width) then the OCXO tuning voltage drops to around 2V when the loop is locked.
It's still around 2V for shorter intervals and widths such as 10msec interval with a 1msec width, 1msec with a 100uS width or 1msec with a 1uS width.

In the case of a 1uS width I can change a jumper such that the monostable is not used and the sampling gate is derived directly from the timepulse.
That makes no difference to the OCXO tuning voltage. It remains at 2V.

The difference between the two OCXO tuning voltages is worrying.
The OCXO has a positive tuning control slope, so the default 1sec configuration must output a higher frequency compared to the shorter intervals and widths.

Any suggestions as to what might be going on?

[nctnico]

On the uBlox module I have used for a GPSDO design, the shorter update intervals didn't seem to work (give weird results). I never really dug into this and chalked it up to a bug. Maybe the shorter update intervals work for navigation only and disable the time synchronisation features. You'd have to ask uBlox what is going on here.