General Purpose Power Supply Design

[amspire]

I have not actually tried to design a CUK converter. Usually the reason is the simpler design is tried first, and if that works, the more complex design is ignored. I might have to see if someone else has experience.

The flyback design is capable of great range and is about as simple as you can get.  I am really working on costs, and I cannot see how a CUK design would not be more expensive.

The initial tests look good, but now I need to isolate the secondary. Looking around for an optocoupler. I thought I had some, but they are all opto-triacs.

I think I better throw together an adjustable current sink for testing the supply.

Richard

[amspire]

I have a isolating switching pre-regulator working and it is looking pretty good. Everything is running very cool.

Tried out the feedback via an optocoupler and it worked first time.

Once I have put together a constant current load, I will do some tests and post the results. It is not the final circuit as I am using just the parts I had lying around.

The UC3842 chip I am using for the moment only lets me test down to 10V minimum input and I want it to work down to 3V DC input, but using different regulator chip will not change the performance of the switching supply much. Currently using a 300kHz switching frequency.

Since I am using it as a pre-regulator, I do not need much accuracy. The current circuit will run at about 1.3V above the linear supply output voltage and I could end up sticking with that.

I hope to post the circuit and test results tomorrow. Once I have fully tested my test supply, I can put together a full Rev 1 design that allows you to take any voltage source between about 3V and 20V and convert it to an isolated 0 to 24V 1A linear supply.

Richard.

[electronwaster]

This sounds great, it sounds like (if I'm not misunderstanding) it can be built without a microcontroller, in which case I'm definitely building one (or a combinable pair) as a lab PSU.

I have been trying to design and build a PSU starting from scratch (no electronics knowledge whatsoever), and so far I have an zener/opamp/pass transistor circuit that can go down to 0V and offers reasonable load regulation, but no constant current limit. You have just provided me with a great shortcut! 

Thank you for your efforts putting this together, I am really grateful!

electronwaster

[amspire]

This sounds great, it sounds like (if I'm not misunderstanding) it can be built without a microcontroller, in which case I'm definitely building one (or a combinable pair) as a lab PSU.

Definitely. It can be fully used without any micro. Also the idea will probably be to do two versions - a through hole version that would be easy to build, and a smaller SMD board. So far all the parts I am using are available in both forms, but I still have to pick the switching regulator. If you don't mind having a heatsink, the linear pre-regulator will be a simpler option and will be noise free. A heatsink probably does cost more then the parts for a switching regulator.

I have been trying to design and build a PSU starting from scratch (no electronics knowledge whatsoever), and so far I have an zener/opamp/pass transistor circuit that can go down to 0V and offers reasonable load regulation, but no constant current limit. You have just provided me with a great shortcut! 

Thank you for your efforts putting this together, I am really grateful!

electronwaster

Thanks for the encouragement.

Richard.

[markus_b]

Thank you for your efforts putting this together, I am really grateful!

electronwaster

Thanks for the encouragement.

Richard.

Mee too !

Contrary to electronwaster I like the microcontroller, but the design allows for both. I'm comfortable to design (and program) the micro, but for the analog and switching stuff I'm lacking experience.

[A Hellene]

Richard, I remember reading an article while I was researching about the efficiency of SEPIC converters, in which was shown that the SEPIC topology is in many ways better than Flyback: SEPIC outperforms the flyback. Not to mention another article, where is shown that SEPIC Converter Benefits from Leakage Inductance.

Now that I finally found some time to play with it, having already a spare ATtiny861A in hand, I constructed a simple test circuit to see how a 16-bit Sigma-Delta PWM loop DAC behaves. I also connected to the t861A an LCD module and a few push-buttons to be changing the 16-bit DAC target value on the fly. Using the t861A Timer1 Compare-A in Fast PWM Mode running at 32 MHz, I observed that:
1. TC1COMPA will start only when the output value is greater than or equal to 0x0081 (129d), and
2. TC1COMPA saturates (PWM output always HIGH) when the output value is equal to 0xFF00 (65280d); beyond that value the output diminishes, since the MSB overflows and the ISR disregards any possible carry bits.

Both of the observations above were expected, since the 8-bit base PWM ISR,
1. Will not fire when the PWM MSB is equal to zero, so there is no update of the error accumulator, and
2. Will have an always high output when the PWM MSB is equal to 0xFF.

The Sigma-Delta extended PWM loop DAC sounds to be a nice idea but, I am sorry, no cigar...


-George

[IanB]

The Sigma-Delta extended PWM loop DAC sounds to be a nice idea but, I am sorry, no cigar...

However, I don't think sigma-delta is your only choice of algorithm. You could use a direct computational algorithm.

For instance, to output 16 bits of precision on an 8 bit PWM you could proceed as follows:

1. The MSB has 256 times the magnitude of the LSB, so output it 256 times.
2. After outputting the MSB 256 times, output the LSB once.
3. Repeat from step 1.

Unfortunately the LSB is going to appear as a "bump" every 256 cycles, so heavy filtering is going to be required to obtain the smooth average value.

[markus_b]

The Sigma-Delta extended PWM loop DAC sounds to be a nice idea but, I am sorry, no cigar...

However, I don't think sigma-delta is your only choice of algorithm. You could use a direct computational algorithm.

I think it may be easier to combine two PWMs one for the upper and one for the lower 8 bits and combine them externally with a resistor network. This requires slightly more external hardware to combine the two PWMs, but the filter remains simple.

[A Hellene]

Ian, I think that you are correct. <8_bit_MSB>*2^8 + <8_bit_LSB>*2^0 (or <8_bit_MSB>*2^16 + <8_bit_NSB>*2^8 + <8_bit_LSB>*2^0, for a 24-bit solution) using an 8-bit hardware PWM stage sounds right to me. However, this raises the complexity of the code and renders all the remaining fast PWM hardware modules of Timer1 incapable of producing a second PWM output, while the test circuit described above is already producing two 16-bit PWM outputs (using the Timer1 Compare-A and Compare-B fast PWM channels) and it has the third fast PWM channel (the Timer1 Compare-D one) free to produce yet another 8..10-bit PWM output.

Markus, this is right in theory; but the external resistor network adder of the two PWM outputs should be of a 16-bit precision in order to preserve the output linearity and avoid any output missing codes.


In my opinion, it will be easier to use any other AVR (of the mega family, for example) with a hardware 16-bit PWM to produce a 16-bit DAC output. But, again, for every 16-bit PWM DAC it will be needed a separate AVR chip.

Since we are not talking about a mass production device but about an one-off solution, I would prefer to use a <10 USD worth Analog Devices or Linear Technology <1 LSB INL 16-bit DAC of 1 MSPS update rate for each Voltage/Current channel, which will additionally offer me the possibility of modulating the PSU output in a user programmable manner, since my initial thought was to add an arbitrary waveform output functionality to my PSU.


-George

[amspire]

The Sigma-Delta extended PWM loop DAC sounds to be a nice idea but, I am sorry, no cigar...

However, I don't think sigma-delta is your only choice of algorithm. You could use a direct computational algorithm.

I think it may be easier to combine two PWMs one for the upper and one for the lower 8 bits and combine them externally with a resistor network. This requires slightly more external hardware to combine the two PWMs, but the filter remains simple.

Combining two DACs to get extra resolution is in general a bad idea. As George pointed out, unless the two are matched incredibly well, you end up with a poor result. My no.1 requirement is a monotonic output and that means a single PWM.

Richard.

[amspire]

The Sigma-Delta extended PWM loop DAC sounds to be a nice idea but, I am sorry, no cigar...

However, I don't think sigma-delta is your only choice of algorithm. You could use a direct computational algorithm.

For instance, to output 16 bits of precision on an 8 bit PWM you could proceed as follows:

1. The MSB has 256 times the magnitude of the LSB, so output it 256 times.
2. After outputting the MSB 256 times, output the LSB once.
3. Repeat from step 1.

Unfortunately the LSB is going to appear as a "bump" every 256 cycles, so heavy filtering is going to be required to obtain the smooth average value.

I actually like this idea a lot, and you do not need heavy filtering. Say you use the atiny with the 64MHz clocked PWM. The 8 bit PWM cycle is 250KHz. With your scheme, an 250KHz/256 = 0.976Khz component will be added. The simple 3 stage RC filter (10k/1uF) I was proposing has a rejection of 1KHz components of  over 100dB. That is excellent.

Ok. I want better then 16 bit resolution, and there is no reason not to go for it.

If I increase the filter to a 4 stage 100K/.22u, then by adding an extra correction every 16 of the previous corrections, I end up with a worse case P-P ripple of 1uV. On average it will be half that. Even with 3 stages, the RMS ripple is less then 1uV.

To put these numbers into context, the output noise due to the LM324 opamp will probably be 1-2uV.

The beauty of this method of correction is that the corrections can be pre-calculated, so all we need in the PWM interrupt routine is two counters. Once every 256 PWM cycles, we use the first correction factor. Once every 256* 16 cycles, we use the second. The rest of the time, we use the non-corrected 8bit PWM value. 

I suspect this could work to give a 22 bit PWM result.

Richard.

Edit: The implementation is slightly more complex - but not by much.  The complication is this. Say the 8 PWM value is "186" and at the end of 256 cycles, we need to add an extra 215 - we cannot get a PWM cycle that somehow outputs  186+215 for one cycle.  We can make sure that for PWM counts below 128, we always need a positive correction, and for PWM counts above 128 we always need a negative correction. Then instead of correcting every 256 PWM cycles, we correct every 128 cycles. It also means the amplitude of each correction is half, that all helps.

As long as it works in the end. I have done this kind of micro work before, and you get it working somehow. Once it is working, it doesn't matter how untidy it looks under the bonnet.

[amspire]

Since we are not talking about a mass production device but about an one-off solution, I would prefer to use a <10 USD worth Analog Devices or Linear Technology <1 LSB INL 16-bit DAC of 1 MSPS update rate for each Voltage/Current channel, which will additionally offer me the possibility of modulating the PSU output in a user programmable manner, since my initial thought was to add an arbitrary waveform output functionality to my PSU.

-George

George everything you say is true, but I am being pretty ruthless with my costs. Any half decent A/D dac with a good monoticity will cost more then all the rest of the main supply board parts combined.  Basically, if there is any way to get a $1 micro to do the job, I will still continue to chase it.

It is fine if the micro is spending 95% of its processing time doing the PWM. I would use a single PWM interrupt to handle both PWM outputs, so that  saves the cycles for one "iret".

In my response to IanB's suggestion, I proposed a 22 bit method that would need two 8 bit counters in the interrupt routine (shared by both channels). The first is incremented every cycle then second is incremented when the first overflows.

Based on the counters one of 3 precalculated PWM values are loaded. This eliminates any calculations from within the PWM interrupt.

The same method would work very much easier with 16 bit PWM, but I don't want to go to a much more expensive processor to get two 16 bit PWM's.  Using two 10 bit PWM's in the ATtiny 861 is worth looking into. It should give more time for the interrupt, even with the fact that two PWM registers have to be controlled instead of one. It would mean that one correction cycle is done every 1024 PWM cycles, and then one secondary correction cycle is done  every 4096 PWM cycles. The rest of the time, the PWM value is unchanging and all the PWM interrupt will be doing is incrementing a 2 byte counter and doing a 10 bit comparison.

Richard.

Richard.

[IanB]

Edit: The implementation is slightly more complex - but not by much.  The complication is this. Say the 8 PWM value is "186" and at the end of 256 cycles, we need to add an extra 215 - we cannot get a PWM cycle that somehow outputs  186+215 for one cycle.  We can make sure that for PWM counts below 128, we always need a positive correction, and for PWM counts above 128 we always need a negative correction. Then instead of correcting every 256 PWM cycles, we correct every 128 cycles. It also means the amplitude of each correction is half, that all helps.

I was scratching my head over this before and I thought I was OK to output the LSB alone on the 257th cycle, but your comment above prompted me to think about what happens when the LSB is 0. In that case the algorithm would have sent a zero every 257th cycle, effectively multiplying the required output by 256/257. So I see you are right, it is more complicated. I don't fancy solving the complication as it's not my problem    but apparently you have it covered.

(However, I cannot stop my brain from trying to solve the complication even when I tell it not to. Silly brain.)

So, if you add 186+215 you will overflow the 8 bits into the 9th bit; in other words 186+215 = 256 + 145. However, 256 neatly divides by 256 and becomes the lowest order bit of the MSB. So all we need to do is add one to the MSB and reduce the LSB accordingly. When MSB = 186 and LSB = 215, we output 187 for 255 cycles and 146 on the 256th cycle.

[BravoV]

I have a isolating switching pre-regulator working and it is looking pretty good. Everything is running very cool.

Richard, if its not troubling you too much, apart from the circuit that you're going to post, please post few photos of that working switcher, this will at least give us a clue how it looks like physically.

Frankly, I'm particularly interested with the transformer and assuming you made it your self.

[amspire]

I am making it myself using a toroid that can be very cheap from the right source. Something like 7c each if I buy a bag of 500.  I am currently using a Micrometals T50-52 core, and I hope I can use an even smaller T44-52 core that is just 11.2mm outside diameter. I am pretty happy with the way the powder core toriod is working at 300KHz so far, and I will probably try increasing to 500Khz.

http://www.micrometals.com/parts_index.html

These types of cores have been used a lot in things like PC motherboards, so I assume that various Chinese manufacturers are making compatible cores by the truckload.

Ferrite cores can be very expensive, so if I can use this cheap one, it will be great. Somewhere out there, there may be a cheap off-the-shelf transformer that would work at an affordable price, but I am after everyday parts, and that transformer will not really fit with that plan. In general, one off prices for SMD transformers can easily be over $10, and I have to test them first before I even know if they will work adequately.

So I am not even trying to find a transformer. If I was a corporation planning on a production run of 100,000+ supplies, that would be different.

I will post some photos, but I still have to finish building my constant current load so I can test the supply at full power out. (My selection of power resistors is not very good). Probably another hour of work to finish the load this evening before I return to the supply.

Richard.

[A Hellene]

I have found a problem. It might be me but I do not think so, since a 1.5c update delay for the asynchronous t85/t861A PWM timer registers is already documented in the data sheets. Let me explain myself:

Experimenting with the Fast (64/32 MHz) PWM of the t861A asynchronous Timer1, I discovered that though I am able to change the PWM output in one Timer1 clock cycle time by modifying the PWM Output Compare Match registers, I can do it only if I am not updating a previous PWM value of 0x00. This means that the Sigma-Delta extended PWM loop, that often needs to load a PWM value of 0x00 and then change it rapidly to something else, will not be able to run correctly due to the extended restart delay of the PWM module after an update of a zero PWM value.

Since I initially thought that this was happening because of an extremely low PWM value loaded, that could not start the corresponding ISR responsible to update the PWM error accumulator, I moved both the PWM output channel ISRs code to the Timer1 overflow ISR, which is always served every 256 timer cycles, regardless of any possible PWM channel being enabled or not. I did that in order to have a means to be constantly updating the PWM error accumulators, independently of the state of the PWM channels. But I stumbled on the PWM module update delay that occurs when the previous PWM value is equal to 0x00... I will try to further investigate this anomaly, since it might be happening because of a possible detail I may have overlooked.

Of course, there is the ATtiny84 with a true 16-bit dual channel PWM hardware module, able of running at CPU speed, that can produce a two channel 16-bit PWM output with absolutely no CPU intervention. Speaking of cost sensitivity, the 2 Kbyte FLASH t24/t25/t261 are more inexpensive than the 4 Kbyte FLASH t44/t45/t461 or the 8 Kbyte FLASH t84/t85/t861 devices.


-George

[amspire]

George, if it helps, I will never be using a PWM value of 0x00 as I am adding some offset.

The reason I need to add some offset is it is essential if I am going to have software calibration - I need to be able to adjust either way near zero.

This is a problem for a design where you were choosing a good reference and high tolerance resistors just so calibration was not needed - in that case you do need 0x00 to be 0V and 0xFF to be maximum volts.

In my case, I want to be able for calibrate for opamp offsets and differential amp errors in my Current measurement circuit, so I will probably be using the PWM range typically from 0x08 to 0xF8.  With calibration, I could get down to 0x04. If there is a problem with low PWM values, I can increase the offset.

Richard.

[A Hellene]

In that case, Richard, I think that the 16/24-bit extended PWM code posted previously is ready to be used! There are no problems at all for PWM values between 0x0100[00]+1 and 0xFF00[00]-1; keep in mind though than the TOP value of the extended PWM DAC is equal to 0xFF00[00]-1 (and not 0xFFFF[FF]), for the correct calculation of the DAC output gain coefficients (I am using brackets for the possible 24-bit LSB of the PWM values).

Speaking of the asynchronous Timer1 PWM update delay I mentioned above, here are the readings of the Fast Mode PWM stage output of the t861A asynchronous Timer1 (set for 32 MHz clock frequency), where one clock cycle time is equal to 30.7 ns (f=32.6 MHz) and a complete PWM cycle period of 256 cycles is 7.87 µs (f=127KHz). The clock frequency deviation is due to the fact that the AVR internal oscillator is factory calibrated for use at Vdd=3.0V, while the test circuit supply voltage was 5.0V. If it is required, the oscillator can be re-calibrated for 1% accuracy over a wide supply range of 1.8V .. 5.5V.

The Fast Mode PWM was specifically programmed to output the following pulse train pattern, in nine discrete steps (where c is the PWM Compare-Match value loaded to the OCR1A/OCR1B registers, while the TOP counter value was set to 0xFF). The readings captured below were synchronised to Channel 2 (blue trace) that was triggered by positive pulses (of a specific width for each case), while Channel 1 (the yellow trace) was testing the PWM recovery time after setting the PWM value to 0x00 at Step 4.


Step 1. Ch2 = 1c, Ch1 = 1c: Correct.


Step 2. Ch2 = 2c, Ch1 = 2c: Correct.


Step 3. Ch2 = 3c, Ch1 = 3c: Correct.


Step 4. Ch2 = 4c, Ch1 = 0c: Correct.


Step 5. Ch2 = 5c, Ch1 = 5c: WRONG!
Channel 1 should be producing a 5c positive pulse.


Step 6. Ch2 = 6c, Ch1 = Unchanged (5c):
The Ch1 5c positive pulse (that was loaded and should had been produced at the previous step) is present now, delayed by one Timer1 clock cycle.


Step 7. Ch2 = 7c, Ch1 = 7c: Correct.


Step 8. Ch2 = 8c, Ch1 = 254c: Correct.


Step 9. Ch2 = 9c, Ch1 = 1c: Correct.


It is obvious that the PWM value of 0x05 at step 4, loaded right after the PWM value of 0x00 at step 3, takes two Timer1 clock cycles to be produced while every other PWM update that does not follow a previous PWM value of 0x00 takes only one. Clearly, this is a problem for a Sigma-Delta extended PWM loop DAC implementation that is expected to produce a sub-MSB value output.

This is what the t861A Timer1 Overflow ISR Handler test code looks like:

Code: [Select]

in r4,SREG ; Status Register preservation
push YL
push YH

; Nine-step PWM output sequence
cpi YL,1
brne PC+2
ldi YH,1

cpi YL,2
brne PC+2
ldi YH,2

cpi YL,3
brne PC+2
ldi YH,3

cpi YL,4
brne PC+2
ldi YH,0

cpi YL,5
brne PC+2
ldi YH,5

cpi YL,6
brne PC+2
rjmp _ReloadB
; ldi YH,6

cpi YL,7
brne PC+2
ldi YH,7

cpi YL,8
brne PC+2
ldi YH,-2

cpi YL,9
brne PC+2
ldi YH,1

out OCR1A,YH
 _ReloadB: out OCR1B,YL

inc YL
cpi YL,10
brne PC+2
ldi YL,1

; Done
pop YH
pop YL
out SREG,r4 ; Status Register restore
reti
-George


EDIT: Corrections and additions.

[amspire]

Sounds like good news George.

Still trying to finish up my Switching preconverter tests. Managed to blow up a Schottky diode on the transformer output, so I will get back to it tomorrow. I need to get this done so I can document the full Mark III design.

Then I think I will do some kind of micro test.  I want to build up a proper filtered PWM and take a look. I have a digital pot somewhere I can use.

Richard.

[jahonen]

Somewhat unrelated implementation work but anyway, inspired from amspire's idea, I did a delta-sigma modulator in an Altera 2C8 FPGA just for interest, and reduced the "PWM" to just 1-bit one. It really does work quite nicely, as I was able to clock the modulator up to 150 MHz. That pushes the noise to quite high at frequency spectrum. I used 24-bit resolution, but that is easy to change in VHDL code. This is definitely a strange combination of DC precision and careful high-speed design. Switching a precision voltage reference in such a high rate does add some complications

I was able to adjust the output in very small steps, some µV or so. But of course, IO voltage supply is not a precision one by any means, so there were quite significant drift.

First test was just a ramp generator, the analog post filter was just 39k/4n7 RC (just some random convenient values without any design) from a junkbox:



I thought about testing that as an audio DAC but didn't bother to interface it to a SPDIF receiver Then I tried adding two inputs which let me adjust the value up and down. I measured the result with Gossen's Metrahit energy after adding second RC stage of 10k/1µ (again, no any design, just a test). As you can see, the result is quite nice:



Of course, there was some drift but the result was still surprisingly good for such a crude and simple circuit.

Here is also the digital signal spectrum measured directly from a FPGA pin (before RC filters).



You can see the notch at 150 MHz, which is the operating frequency of the modulator. That reminds me that some pre-filtering is probably useful, as the attenuation of a "low-frequency" filter tends to suffer at higher frequencies due to nonidealities.

Regards,
Janne

[A Hellene]

Ah! The wonders of the 1-bit DAC! With one only imperfection: The digital output stage limitations of reaching the true Vdd and GND levels, while hunting down 0.06 ppm accuracy of the 24-bit requested resolution... But then again, is there any other way of pursuing such goals?

Very nicely done, Janne!


-George

[amspire]

Janne,

It is pretty amazing seeing the results of your 1 bit PWM. The fact you were able to adjust it to 50.000mV on the meter means you must have had surprising good stability, especially when you consider the clock frequency.

It is very encouraging to see this. With 24 bit resolution, that means you need you need a RC time constant of about 0.1 seconds, so two stages of 100K/1uF RC filters would give a really clean result. That should reduce the PWM noise to well below the 1uV level.

Richard.

[BravoV]

Although I can't contribute much on this, just want to say currently this is one the best thread in this forum.

Keep up the excellent works, really appreciate the contributions made.

[amspire]

Thanks. I will start the posts on the switching regulator design - just haven't had much time last few days.

Richard.

[A Hellene]

I cannot explain my persistence for the implementation of a 16-bit PWM DAC. Maybe it is because the tiny24, which has a true 16-bit dual channel PWM (like all the mega's), costs USD 1.01 a piece in single quantities from Digi-Key and because a dual 16-bit PWM DAC is monotonic by principle; so, in that regard, it is more accurate and better than most of the 12-bit "affordable" stand alone DACs. The beauty of this implementation is its simplicity: You just set it up once and you forget it! The CPU spends all its time in sleep mode, with an overall consumption of less than 5mA (or less than 2.5mA for the Pico-Power parts). Should you need to change any of the outputs, you just modify a 16-bit register pair for each channel and you are done: The hardware takes care of the PWM internal elements update in order to avoid any output glitches!

In the example below, the PWM frequency is set to 8 MHz (a compromise of output update speed and chip current consumption), which gives a full 16-bit PWM cycle time duration of 2^16 * 125ns = 8.192ms. 1 LSB represents a 76.29 µV step for Vdd = 5.0 V (5V/2^16LSB) or a 50.35 µV step for Vdd = 3.3 V or a 41.20 µV step for Vdd = 2.7 V. For the output filter component values I did not even pull a calculator; I just used a simple two stage RC filter of 15K/0µ1 (multilayer) for the first sweep and of 15K/1µ0 (tantalium) for the second one.


1. 16-bit PWM sweep with a 2-stage output filter of 15K/0µ1


2. 16-bit PWM sweep with a 2-stage output filter of 15K/1µ0

I ported the tiny861 code above to a mega88 I have already had in hand and programmed it to output the sweep above, for the codes 0x0000 .. 0xFFFF. Well, not exactly for all the codes because 2^16 steps of 8.192ms per step takes 537 sec and it would take ages to plot; what I did was to increase the PWM code by 32 LSB (8.192ms * 2^16/32 = 16.8s) on every 16-bit PWM cycle completion; much better now!


-George