General Purpose Power Supply Design

[A Hellene]

Richard, the AVR "32 general purpose registers" is the processor's Register-File, i.e. the special SRAM registers the ALU has direct access to. It is what the older 8051 and the PIC architectures call the Accumulator/Working Register, with the difference that in the AVR it is not a single register but a whole set of 32 registers. You can see that this is the same approach of the MSP and the ARM, for example, family processors that have a register file of 16 uniform registers. In the AVR, everything beyond the Register-File and before the SRAM space is called I/O space and is used to be accessing the microcontroller's peripherals.

The AVR Register-File is not a uniform one. It consists of the low (r0..r15) and the high (r16..r31) registers. The low registers cannot handle immediate values; the high registers can. The first bottom register pair (r1:r0) is also used for the storage of the hardware multiplier 16-bit product. The four top register pairs (r25:r24, r27:r26 or XH:XL or X, r29:r28 or YH:YL or Y, and r31:r30 or ZH:ZL or Z) have 16-bit addressing capability for the 16-bit ADIW and SBIW math instructions. The three top register pairs (X, Y and Z) can be used for indirect addressing of the whole SRAM/EEPROM spaces and the top register pair (Z) can also be used for the indirect access of the FLASH memory space.

Why is the large Register-File important is obvious, since it eliminates the need to be constantly accessing the SRAM space in order, for example, to deal with multi-byte figures, since almost every instruction that accesses the register file takes one CPU cycle only, while the direct access of the SRAM registers takes two.


I hope this helps,
-George

[A Hellene]

Richard, in order to realise the benefits of a large Register-File, I took the time to rewrite the TIM1_COMPA/B/D ISR I posted previously, using exclusively registers of the AVR Register-File. Please, notice that this is a real world example and not an Academic demonstration of the AVR capabilities.

Code: [Select]

; This is the ATtiny861 PWM Timer1 Compare-A ISR handler (in Fast PWM Mode), where:
; * r2:r0: 24-bit PWM target output value, MSB first
; * r5:r3: 24-bit PWM error accumulator, MSB first
; * r15: Used as a temp to preserve the Status Register
; * OCR1C holds the Timer1 TOP value, which must be set equal to 0xFF
; * TC1H (the 10-bit Timer1 high byte) is set equal to 0x00; or else set it to zero before the update of OCR1x
; For the Current reference output 24-bit PWM ISR there will be needed another similar set of 3+3 registers
;  for the second PWM Timer1 Compare-B/D ISR handler, while r15 can be reused for the same task.

in r15,SREG ; [+3c] Preserving the CPU Status Register
; --Magic part #1:
out OCR1A,r5 ; [5c] Send the top byte of the PWM error accumulator to the PWM for the next cycle
; --Magic part #2:
sub r5,r5 ; [6c] Subtract the byte sent to the PWM from the top byte of the PWM error accumulator
; --Magic part #3:
add r3,r0 ; [7c] Add the target output value to the error accumulator remainder
adc r4,r1
adc r5,r2 ; [9c]
; Done
out SREG,r15 ; [10c] Restore the Status Register
reti ; [15c] (= 1.875µs @ 8 MHz)
You can see that the same function has now become three and a half times faster than in the previous implementation! Using the same CPU and Timer1 clock frequency of 8 MHz, it now takes only 1.875µs for the ISR to complete against the 6.50µs previously needed! The obvious penalty is the loss of the registers r5:r0 and r15, that cannot be used anymore for anything else; but this is not really an issue because the processor has 25 general purpose registers left to use for other possible tasks! Isn't AVR a lovely chip?


-George



<EDIT>: Last minute corrections and clarifications...

[amspire]

Thanks for the explanation George. What  I found incredible is that the data sheets do not explain this well at all. No nice memory mapping diagram. It has a command summary full of letters like k, P, Rr, etc but they don't explain what the letters are.

There is probably a document somewhere that does explain this, but finding that document is not easy.
I have never touched Atmel assembler before and struggling with the data sheet was just odd. I was thinking there has to be general purpose registers, but where?  They are not in the "Register Summary". They are not in the Memory  section of the datasheet. Older processors like the 8051 used to explain all this extremely carefully, but Atmel can't be bothered.

In your first code, you use A1, A2, etc.  Other code uses R1, R2, etc. I assume they are the same?

Richard.

[amspire]

Hi amspire , i've been following Dave's PSU design and got the same idea, because i'm not very handy with microcontrollers , but i didn't find the time to try to make it "analog". The switching pre-regulator it's a great idea, but i
was stuck trying to find a simple way to control both regulators from an unique Vset potentiometer.

The heart of this design is a very cheap board that can be controlled totally from potentiometers if you do not want to use microprocessors. I am making sure that none of the functionality is affected if you leave out the micro. I know that trying to get a micro programmed when you are not set up for it is not fun.

By the way i've got a cup of questions :
how you make this regulator go down to 0Volts?  negative control voltage ?

There are two parts to this. First getting 0 volts out is easy -if you reduce the current you are supplying down to zero, you have zero volts out.

Secondly is how you actually regulate down to zero volts.

The LM324 opamp inputs can actually work to a little below the negative supply rail. They do this with a clever design using PNP input transistors. A PNP transistor can still be working with the base at -0.1 volts and the collector between zero volts and +0.5 volts.

Are you aiming to make it portable?

If you put the board in your own box, it can be portable.  It will run of a 12 battery perfectly, but you would have to add a charger. The control panel version may end up being not portable, but I have other issues to work out before I get serious with the packaging.

Richard.

[A Hellene]

Richard, in the AVR assembler you can assign label names for everything. The original names of the Register-File members are r0, r1, r2, ..., r30 and r31. Since I almost always have to deal with 32-bit or longer figures, I usually rename sets of consecutive registers in order for the code to be easily readable. Regarding the A0, A1, etc. nomenclature I used previously, I just offered the convenience of using any registers available, as I explained it at the header.

In the assembler you can directly use the name "r15" or "R15" to access r15; but since, for example, I usually have a null value register (always loaded with the constant 0x00) I prefer to call it "Zero" instead of r15. Or "tmp1" and "tmp2" instead of "r16" and "r17." Specifically, I usually call A3:A0 the registers r21:r18, B3:B0 the registers r25:r21, etc. But this is only me! There are not any global rules that work for everyone; you just pick a style you are comfortable with and works for you.


-George



<EDIT>
Edited to say that I rather prefer to work with the "mature" AVR Studio 4, which can be found here (v4.19.720), that with that ugly creature they call AVR Studio 5...

[amspire]

George, your latest code is probably useable, so I think I will drop my more complicated solution. We can get two PWMs going with a 32MHz clock. I probably need the option of running at 2.7 volts anyway.

I gather that any other interrupt routines will have to reenable the PWM interrupts as the first command.
Any further PWM outputs still just have to be plain 10 bit PWM.

If it is any use, there probably are some I/O registers we can pinch for other duties. I doubt I will be using the timer0 PWM registers or the dead time register.

Richard

Edit: I am happy loosing some general purpose registers to improve the interrupt speed. The micro will not have a lot of tasks to do.

[A Hellene]

Well, these are a few quick thoughts:

According to the data sheets, at 2.7V both the t85 and the t861 can run at 10 MHz CPU clock frequency and their high-speed timers at 64 MHz. Since the t861 has a three-channel 10-bit hardware fast PWM stage and t85 has a two-channel 8-bit one, this rules out the use of the latter chip. What worries me is the unavoidable noise induced by the CPU/Timer digital stages transitions and the jitter of the RC/PLL clock generators that affects the output linearity. I am afraid that I am not even sure if a decent 16-bit linear output is feasible, where 1 LSB = 41.20µV; this is getting much worse for a 24-bit solution, where 1 LSB = 160.9nV...

Now, the AVR can execute nested subroutines on demand (by the manual enable of the global interrupts flag within the Status Register, at some point within an ISR) but why do that? The idea is to finish the critical ISR code execution as soon as possible and not to extend it any further. But this can be arranged in favour of preventing output glitches in the case of an interrupt firing while another ISR is executed.

After booting up, the firmware initialises the hardware modules and their variables, it starts the PWM modules, enables the global interrupts and enters the main, where it does nothing else than sleeping to reduce power consumption while waiting to receive from the serial line any further commands and/or new values for the PWM modules. The SPI protocol seems to be better for synchronization purposes, since the CPU workload is not negligible in this application.

The latest ISR code above will need 1.875µs for the completion of the extended PWM ISR, which means that 256 timer steps (a complete hardware PWM cycle) should not take less time than that figure, which implies that the PWM clock tick should be no less than 7.32 ns or its frequency be no more than 136 MHz. So, we are good running the PWM timer at full speed. These figures even allow us to add a second extended PWM ISR if we reduce the PWM speed in half.


-George

[amspire]

The other thing is if we move to 10 bit, we get a time gain of four, so even though there will be some extra code, it is probably OK.  I will take a look at the PLL stability spec, but with al the filtering, it will probably be OK in the end.

Linearity really isn't a concern, as the truth is every time someone wants a really accurate output, they will use a multimeter. 1% accuracy is all you need for general use, and I am sure we can do better then that. We should get a monotonic output though which is my no.1 demand.

Richard.

[hlavac]

Guys, why do you concern yourself about the ISR length? The 64MHz is PWM CLOCK, not PWM frequency, that will be 256 times less for 8-bit PWM, or 250kHz. Plenty of CPU cycles - you can run CPU at 16MHz (Pclk/4), thats 64 CPU cycles per one PWM cycle/interrupt, more than enough...
And as for the supposed glitches, the PWM registers are double buffered to avoid just that (i.e. whatever you write will affect the next cycle, not current cycle).
At least for the ATtinys I'm familiar with...
I would keep the PWM stuff in interrupt as is and do the SPI reading/target value setting in main loop via polling, no need of nasty interrupt nesting.

[amspire]

Guys, why do you concern yourself about the ISR length? The 64MHz is PWM CLOCK, not PWM frequency, that will be 256 times less for 8-bit PWM, or 250kHz. Plenty of CPU cycles - you can run CPU at 16MHz (Pclk/4), thats 64 CPU cycles per one PWM cycle/interrupt, more than enough...

And as for the supposed glitches, the PWM registers are double buffered to avoid just that (i.e. whatever you write will affect the next cycle, not current cycle).

We have been working with these numbers. We need two PWM's and that is when it gets very tight. About the glitches, there things that we have to watch out for. For example, triggering off a match means the code can run before the next match. However, it may not complete before the next PWM cycle starts, and so double buffering means that the new value does not get run till the cycle after.

Probably triggering of the end of the PWM is best. That means the one interrupt will process both PWM's at the same time, and that saves a few cycles as well.

At least for the ATtinys I'm familiar with...
I would keep the PWM stuff in interrupt as is and do the SPI reading/target value setting in main loop via polling, no need of nasty interrupt nesting.

That sound like a good plan. The micro really does not have much to do.

Richard

[A Hellene]

Richard, moving to a 10-bit PWM is even easier: You just set the module up once and you literally forget about it because everything happens in hardware with absolutely no CPU intervention! The t861 Timer1 has a three-channel 10-bit hardware fast PWM stage that needs no maintenance at all after having it initially set up. You only have to modify a couple of registers (TC1H:OCR1x) in order to change its output.

Speaking of the PWM output, it is monotonic by principle: There are no magic value quantities to be added to/subtracted from, that must be exactly equal to the next_value - 1 LSB to the previous_value + 1 LSB; and the length of the output pulse is directly proportional to the OCRx input value, which is a promise for good linearity. There are not any "missing codes" in this topology. But I do not know what happens in these expanded PWM cycles, where the target RMS output is produced by non symmetrical pulse trains.


hlavac, there is a concern of the ISR code length because the CPU runs at 8 MHz and the ISR at 250 KHz (= 64MHz / 256), which leaves a 4 µs time window for the ISR code to do its magic. In 4 µs time, the CPU has 32 machine cycles (which is 32 CPU clock cycles for the AVR) to do what it needs to be done, while the code above (which I do not consider to be final) takes 15 of them for every extended PWM channel. Yes, this is not a tight situation exactly but the previous implementation of that ISR needed 52 cycles and could not be run at that high speeds that do not require heavy output filtering and are faster in response. Neither would I like to raise the CPU frequency to 16 MHz because the current consumption would almost be doubled and the AVR needs to be powered by an accurate source that usually does not (and should not) deliver much power. We agree, though, in the polling SPI implementation, especially since the tinies do not have a dedicated SPI controller as the megas do.


-George

[A Hellene]

Since we got into the business of counting cycles, I discovered a few mistakes in my calculations above.

The ISR execution response time is not 3 (this is for a subroutine call) but 4 CPU cycles plus another 4c if this occurs while the AVR is in sleep mode. This makes the time duration of the ISR above to be not 15 cycles but 16c. Now, the worst case scenario is both the ISRs to fire simultaneously while:
1. The AVR is in sleep mode. This extends the 16c time by 4 more cycles.
2. The AVR executes a multi-cycle instruction (a 4 cycles "return," in the worst case), where that instruction will be completely executed before the pending interrupt is served. This extends the 16c time by 4 more cycles.
Notice that when the AVR exits from an ISR, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Under these conditions, the total time needed for both the ISRs to finish will be 4c+16c+4c+16c = 40 CPU cycles plus 1c uncertainty due to the asynchronous nature of the high speed PLL clock. This requires the complete hardware PWM cycle (not the extended one) of 256 timer steps to be taking no less than 41 CPU cycles or, given that the CPU clock is 8 MHz, no less than 41*125ns = 5.125 µs, which is translated into a PLL clock speed of less than 49.9 MHz. The next acceptable PLL clock frequency is 32 MHz, which results in an 8.0 µs 8-bit hardware PWM cycle, in a 2.048 ms 16-bit extended PWM cycle and in a 524.288 ms 24-bit extended PWM extended cycle. This will need some serious filtering...

I think that the most viable option will be a dual 16-bit PWM with low pass filters of a couple of hundred milliseconds settling time to filter out the 2 ms PWM cycle irregularities.


-George



<EDIT>

Since the t861 Timer1 has a 10-bit hardware PWM, a 32 MHz clock will result in:
1. Setting the Timer1 TOP count to 511 (i.e. 9-bit PWM resolution) results in a 16.00 µs 9-bit hardware PWM cycle and in a 8.19 ms 18-bit extended PWM cycle.
2. Setting the Timer1 TOP count to 1023 (i.e. 10-bit PWM resolution) results in a 32.00 µs 10-bit hardware PWM cycle and in a 32.77 ms 20-bit extended PWM cycle.

After all, this set up does not sound to be that bad...

[amspire]

I suspect the filtering at 32MHz with a 3 stage RC filter is much better then you are expecting. I will definitely give it a go, but I will not return to 16 bit PWM.  Just not good enough.

I might have to do a properly designed filter to get a bit more from the 32 MHz then the very basic RC filters can do. I am sure we can make it work. George, I am totally grateful at all your help so far. It is this kind of detail that takes more time then you think.

Right now I am working to see if it is possible to add a switching pre-converter without making the supply too noisy. If you attach a scope to a circuit under test and see switching noise, it is just not going to work. If I can get the switching supply to work, I totally solve heat issues, allow the supply to run from a huge range of voltages, and I get isolation from the supplies (it is a transformer based switching supply).

I am going to put together a test supply tonight and tomorrow to at least check my choice of a particular toroid can work over the range at full power, but I am sure I will have to do some more design work on the transformer to keep the noise away from the secondary.

Again, I am looking at economy. I want the BOM for the basic supply board and pre-regulator to be under $20.  SMD transformers can be very expensive, and they still may not be right. I have found a small toroid core I can get very cheap, and there are not many turns, so it hopefully will not be hard to make.

Richard.

[Alex_arg]

ahh , of course!  thanks for the clarification Richard, i was not thinking in the adjustable current, and all supplies i've built have negative supply to achieve cero volts..(and for the OpAmps) Good luck   

[BravoV]

Richard, I know its still in very early stage, just curious on your choice for the power switching part ? or maybe the potential list of switcher ic candidates that you're going to experiment ?

[amspire]

I am building a test switcher with the wrong IC - it is just one I happen to have. A UC3842 which stops working when the input voltage gets down to 10V. It will be enough to get the measurements I need. The reason I need to do testing is that a 3 to 20V input, and a 3 to 27 volts output is a huge range if I want to get a full 1A out for every input/output combinations. I may have to cut the input range back to 10V to 20V. That range means old PC supplies could be used as a power source.

3V input would allow a single Lithium battery to be used, but to get 1A out at 25V, a 3V lithium cell would be outputting about 13A. For people who wanted to make a small 200mA supply, currents of up to 2.5 A peak from the cell sound a lot better.

To get the full range of input and output, I am using a flyback design. I want to get it working to test out the transformer and the secondary circuit. With the peak current that is the result of the big voltage range, I probably have to use a controller with an external power MOSFET, but I am not going to choose a regulator until I have a good feel for the frequency I need and I have worked out the transformer details. It is a spare time job, but I might get a few days to work on it this week, which will be good.

Once I know where I am going with the switching pre-regulator, I will put together something summarizing all the ideas, but to give a preview, the main reason I want the boards to be fully isolated from the power source is that I am designing the 25V 1A supply boards so they can run in parallel or serial in a master-slave configuration. So if you want a 25v 5A supply, just put 5 boards in parallel. If you want 100V 1A supply, put 4 boards in series. Or if you want a 100V 5A supply, then I know you are crazy - but why not? It is only 20 boards. 

What I discovered is it is probably impossible to come up with a general purpose design for a single regulator that could be scaled from a 100mA supply to a 10A supply without a redesign. But I can make a single fixed size board that is highly versatile and configurable.

I am borrowing the series/paralleling idea from the old HP supplies, but it is one of those ideas I will have to test for real. No reason why it shouldn't work though. 

If you are building a bigger supply, you could use a PC power supply as a source. One of the compact-sized PC supplies (200W - 350W) is still pretty compact,

It may sound odd, but the thing is if each board is very cheap, it will probably end up being a much cheaper and quicker way to get a supply going then trying to custom design a dedicated supply. It is quite possible that the BOM of the parts for a board excluding the PCB will be under $10. All the parts are easily available through hole, so it is possible to have a through-hole kit - not that I have any real plans at this stage.

It is possible that I can get the board over 1A, but the first rev will be 1A to be conservative. Don't think I want to go above 25Volts. 30V is technically possible, but it is getting too close to the opamp limits for my liking.

There will also be an option of a linear pre-regulator with a heatsink, so you can put the board in a box with with a transformer.

Richard.

[BravoV]

Richard, I really wish your modular design can work with two versions of switching pre-regulator for two kind of sources which are battery powered (step up and down) with much lower current capability, and the 2nd version with higher current source like pc power supply or even step-down transformer (step down only).

[amspire]

If you are planning on battery operation you may want to look into a sepic converter for your preregulator. There is one here.

http://panteltje.com/panteltje/pic/pwr_pic/

Thanks for the link. Sepic converters have been one of the options I have been looking at. I will finally power up my test flyback transformer converter today. Took longer then I was hoping just because I needed a pretty good layout to have a chance at low noise. If the isolated option turns out to be just too noisy, a non-isolated sepic controller design will probably be my next choice.

I am sticking to the linear output stage, just due to the fact it perfoms better then a switching supply output.  The circuit in the link has a 2000uF capacitor on the output and that will be needed to get reasonable regulation, transient response and reasonably low noise on the output. The problem with that is even if you set the current limit to 10mA on the supply, then if the circuit under tests shorts the supply, then all the energy in the 2000uF cap goes into the component shorting the supply and that can damage the very circuit you intend to protect. A good linear supply can give better regulation, better current limiting and better transient response with only a 10uF cap on the output. 

Richard.

[amspire]

Richard, I really wish your modular design can work with two versions of switching pre-regulator for two kind of sources which are battery powered (step up and down) with much lower current capability, and the 2nd version with higher current source like pc power supply or even step-down transformer (step down only).

Definitely something like a 100mA supply is all you need for testing circuits like microcontroller and opamp circuits - very useful. Or a 1A 0-5V supply that decreases to 100mA at 20V out. When I get to the stage of have some working preregulators, I will look at how to organize the different options to make it understandable. I know if you give too many options, it just gets too confusing.

Richard.

[amspire]

Not trying to nit-pick here but if your load is shorting out isn’t it safe to assume its already destroyed and therefore it is the regulator you are trying to protect. If you have multipile loads on the regulator if one shorts out, the voltage after the pass device will still collapse no matter how fast your current limiting is if that’s the concern. That’s how current limiting works.

No. The short can be from wiring faults, from say a switching regulator circuit you are debugging that switches hard on, from a transistor bridge ciruit or audio amplifier output stage where both transistors turn on at the same time - lots of reasons. The diea of current limiting is  that you do not blow anything up duing the debugging.

Yes you are definetly better off using a post regulator not only for noise attenuation but it will ease the magnetics desighn. You may find it to be benificial to use some type of frequency foldback at lower output voltages (powers) where you would be likely to change operating modes from DCM to CCM. A wide input will definetly add to the complexity. May be worthwhile to add a boost to feed your flyback a regulated input.

You are right about the fact that to get a supply working with a wide ranging input and output voltage and current range, I will have to switch between the CCM (a continuous current through the inductor/transformer) and DCM (the inductor/transformer current drops to zero during the discharge cycle) modes.

At high input voltage at minimum volts and amps out, the supply regulation circuit will force a lower switching frequency anyway without an intentional frequency foldback circuit.  The regulation circuit will just not allow the supply to switch again till the output voltage has dropped below the regulation voltage. If there are regulators that implement a deliberate frequency foldback scheme, I would be interested to know about them.

Richard.

[amspire]

No. The short can be from wiring faults, from say a switching regulator circuit you are debugging that switches hard on, from a transistor bridge circuit or audio amplifier output stage where both transistors turn on at the same time - lots of reasons. The idea of current limiting is  that you do not blow anything up duing the debugging.

Sorry but again I'm not following your reasoning for this. You can't control both CC and CV simultaneously. If you have too fast a CC loop then it could prove to be a nuisance.

No, it is not that much of a problem. In normal use, the power supply is not near the constant current limit, so the constant current circuit is hard off. It is tricky getting the supply totally stable right at the precise point where both controls are active at the same time. this crossover window though is extremely tight -  a windows of a few microvolts and a few micro amps, so a problem there is rarely a big problem. The constant current loop has to be pretty fast.

You are right about the fact that to get a supply working with a wide ranging input and output voltage and current range, I will have to switch between the CCM (a continuous current through the inductor/transformer) and DCM (the inductor/transformer current drops to zero during the discharge cycle) modes.

At high input voltage at minimum volts and amps out, the supply regulation circuit will force a lower switching frequency anyway without an intentional frequency foldback circuit.  The regulation circuit will just not allow the supply to switch again till the output voltage has dropped below the regulation voltage. If there are regulators that implement a deliberate frequency foldback scheme, I would be interested to know about them.

Richard.

I think there are some but what I am doing using the cmos version of the UC384x series is clocking it from a PIC10F. If you control the duty of the clock via a PIC you control the maximum duty of the controller thereby limiting maximum power transfer. If you also provide a regulated voltage in my case to an asymmetrical flyback halfbridge via a APFC this allows for pretty precise power limiting or a lot more precise then wide input. My idea for frequency fold back is just to use a Flip flop to divide by 2 the frequency when the voltage, power demand drops below a certain level.

I am testing with a UC3842, but it does have the problem that is shuts down at 10V. How are you changing the clocking frequency without affecting the Rt/Ct ramp amplitude and shape?

Richard.

[amspire]

You have definitely given me ideas about getting a big range. It is possible to just let the regulator cope with very low loads by triggering for a few cycles till the voltage is too high and then shutting down till the voltage is too low again, but changing the frequency lets the regulator run in a more predictable way - probably with much better regulation.

Definitely worth a look. Thanks

Richard.

[robrenz]

This is the type of peaceable constructive community brainstorming that makes this forum great! Keep up the good work

[king.oslo]

Richard, I am impressed.M

[BravoV]

Richard and probably to Achmed as well, not to derail the current discussion and also I'm aware you're working on fly back topology, just for curiosity sake, why Cuk converter topology is not popular since it has excellent ripple output ?

Cause I've been thinking since we're going to wind our transformer anyway. Regarding inverted output of Cuk converter, CMIIW this should not be a problem for this purpose right ?

PS : I don't have any experience in this Cuk, its just I've been reading quite some literatures about it, and it seems like implementation of this topology is quite rare.

Apology if this is way OOT.