High power PFC - choice of topology and key components

[Kremmen]

I am in the process of designing a ~2kW full bridge SMPS. Right now i am working on the PFC front end and one design goal is of course minimizing the dissipation of the switch components.
I haven't locked any of the circuit parameters yet but kind of default assumption is that the rail would be 400VDC  making the average current at nominal power to be 5 A + losses. With that in mind i have made some initial choices. The PFC topology would be boost as usual, and the switch maybe FCH74N60 or similar and rectifier a SiC Schottky diode, probably something like Infineon  IDW10G65C5. So far so good.

To reduce the voltage stress on the smoothing caps and ease component selection there, another possibility would be to lower the rail voltage to say 200 VDC. Now we get to the point; increasing the current will increase losses in the switches and my question is, if anyone has come across a) an optimized PFC topology for these power and voltage levels and b) does anyone have a clever suggestion for a synchronous rectifier circuit to replace the boost diode. I can come up with functional high side circuits myself but they all have the drawback of becoming a bit complex and cumbersome. So if anyone has done this with good results, i would be most interested to hear about it, or good ideas in general.

[Kremmen]

Thanks AcHmed for a very useful reply.

First: no, i am not really going for universal input - this is for EU single phase line power i.e. 230VAC 50Hz nominal.

At these power levels only CCM mode in the PFC would make sense to me. Also, i will do all my own magnetics as well; it is too much of a pain in the ass to try and find suitable ready made components that will be slightly off anyway.
For the 400 V rail i am definitely thinking SiC Schottky diodes, but just because of the increased losses for the lower voltage alternative, i wanted to ask about synchronous options for the rectifier. But it starts to look like i will go with the 400 volt rail anyway, probably makes life easier on the whole.

I too have briefly thought about interleaving several boosters to reduce the loading of individual components. However, due to the nature of the thing i have not discovered how it is possible to separate the PFC phasing and thereby reduce the capacitor ripple. What i mean is, the input current is supposed to be in phase with the input voltage to maximize power factor; that is the reason of existence of a PFC. Now, since the supply is single phase, all "interleaved" sub-PFC's would have to actually be in phase, thereby defeating the interleaving idea. Or am i missing something here?

I have oscillated between 65 and 133 kHz myself without firmly committing to either yet. The higher frequency would bring smaller magnetics but what experience do you have regarding relative switching losses and other tradeoffs between the two frequencies?

[penfold]

At that kind of power rating you would be a lot better off considering an interleaved boost converter topology based PFC.
You would be putting that single switch through a lot of stress. By reducing the power per magnetic component you can probably make them a slightly more realistic size for a lower switching frequency.

[SeanB]

Interleaving is to have the PFC subunits each switching not at the same time as the other, if you have 2 then as the one is starting a pulse the other is ending a pulse. With 3 then you have a 6x high frequency master clock divided by 3 and then divided  by 2 to feed each converter, so that the 3 clocks are 120 degrees apart, so that each subunit handles only 1/3 of the full power, but all sum together draw and output wise to give correction. Capacitor ripple current then is 1/3, and at 3 times the switching rate, with a lowering of the need for current handling in it.

[Kremmen]

Again, thanks all for good commenting.

At that kind of power rating you would be a lot better off considering an interleaved boost converter topology based PFC.
You would be putting that single switch through a lot of stress. By reducing the power per magnetic component you can probably make them a slightly more realistic size for a lower switching frequency.

Yes, my thoughts as well. In my previous post i worried about the method of interleaving. For a 3 phase supply you would have a natural 3 way interleaving but that does not work for 1 phase supply, so the interleaving must be "artificially" phased by the controller. That will be interesting - maybe a 3 phase inverter control scheme can be adapted to serve here. I will look into that.

Interleaving is to have the PFC subunits each switching not at the same time as the other, if you have 2 then as the one is starting a pulse the other is ending a pulse. With 3 then you have a 6x high frequency master clock divided by 3 and then divided  by 2 to feed each converter, so that the 3 clocks are 120 degrees apart, so that each subunit handles only 1/3 of the full power, but all sum together draw and output wise to give correction. Capacitor ripple current then is 1/3, and at 3 times the switching rate, with a lowering of the need for current handling in it.

Yes, i guess i'll have to accept the requirement to create a sync circuit like this. Fortunately 3 phase power and the associated control strategies is familiar territory so as i noted above, this will be my plan A at this time.

I have no experience with interleaved PFC I just ran across it while researching my own PFC. It seems to be doable though how precisely I’m not sure. If I ever need a multi kW pfc it may be worth looking into.

You create a sequencer with evenly spaced phase progression; as many phases as your interleaving scheme calls for. A master controller then governs the switch D for all phases same as in a single phase system. This far it is easy, but the devil will be found in the details, as always.

www.ti.com/download/trng/docs/seminar/Topic5MO.pdf

For me going from 65kHz to 133kHz was mainly necessity to use the magnetics on hand it was the best power to size ratio for what I have. This doubles the driver switching losses naturally for the same fet but still only about 140mW, of course you will be needing some larger fets (possibly paralleled) probably 2 to 3 times the gate charge as mine. Actual losses from commutation I didn’t really evaluate (just thermocoupled the cases) but the use of SIC should greatly reduce fet switching losses as the fet doesn’t have to eat the reverse recovery current.

I'll have to do the math to see if it is worth going to 133 kHz if i end up interleaving the switches. ANd then there is the question if suitable controllers are to be found in the first place.

The main difficulty for me is the magnetics. Operating at 133kHz means for full skin penetration I need to use AWG about 26. Given the RMS current 4.7A 120Hz and then about 1.6A pk-pk 133kHz ripple this is a little impractical, litz is to expensive for a one off. I’m operating under the assumption that if the HF ripple current is kept relatively small and I wind 24AWG in bundles so as to provide a wide surface area for the HF current it should minimize the losses. The other thing I’m going to be trying is spacing my windings above the gap to keep them out of the high intensity fringing flux (1.5mm gap) this is a high loss area (hot spot). Of course when you do this it causes more stray flux but hopefully a bellyband will contain most of it.

Yep, exact same questions i am working with right now. It is starting to look like the higher frequency magnetics is not going to be worth the extra effort. I even looked into hybrid litz-solid wire winding strategies but that will be impractical in real life. Can't be bothered with such tricks. Fringing fields are turning out to be a pain, i still haven't fixed the core geometry to my satisfaction. And this phased booster of course will take everything back to the starting line. But it wouldn't be fun if it was easy, eh?

The original coil craft core was designed for 300W 133kHz. I was running it at 65kHz but reduced output Voltage but deep CCM winding losses dominate so really the inductor should have been operating cooler. The appnote for that inductor shows temperature rise of 105C for the inductor windings at 300W 133kHz. I think the coilcraft inductor has too few parallel windings and possibly excessive gap.

Just the reasons why i won't be looking for ready made magnetics for this.

[Kremmen]

Interleaving is my plan for the Flyback’s. I’m using a micro to generate clock pulses for 3 UCC3843’s . There is one thing that I don’t quite understand about the concept. For say three phases they say the best phasing is 120 degrees. To me it would seem more beneficial if you over lap the duty cycles. Rather then wait until the first switch turns off turn the second switch on at about 50% through the first pulse then flip the third one on when the first one flips off 50% through the second pulse….. This to me would seem to increase the DC component and reduce the AC ripple on both the input and output capacitor. I’m guessing there must be a reason why I haven’t seen this done?

SLUP231 Shows a slight conduction overlap between the two phases. Can you think of any reason as to why you couldn’t overlap even more because I can’t? Would it not be more beneficial or am I missing something?

Think cyclical. In power engineering everybody pictures the AC polyphase power as voltage and current vectors rotating in some coordinate system. Same thing here; your individual boosters are cyclically phased around the full 360 degrees ( or 2pi, if you think in radians). The only spacing that makes sense is an even one, otherwise you will have shorter and longer gaps between phases/pulses in the time domain. So for 3 phases the natural and only phasing is 120 degrees apart. For 2 phases, 180 degrees and for 4, 90 and so on and so on.
Pulse overlap then just follows from the number of individual phases and the pulse duty cycles (D). I don't immediately see why the pulses couldn't overlap considerably. At least electrically there should not be a problem.

Right now i am also thinking of generating the phase sequence using a microcontroller, possibly an ATXMega. Another possibility would be to use a CPLD like Xilinx CoolRunner II but those want all kinds of core and I/O voltages that i may not have the energy to bother with. So, we'll see. I have some of those left over from a previous project so maybe i will think about it though.

[Kremmen]

Managed to find an actual chip from TI http://www.ti.com/lit/ds/symlink/ucc28070.pdf for multiphase PFC. What is even more interesting it has external clock syncing. This would indicate that you can cascade these controllers to create possibly arbitrarily many phases. I would prefer this to a software solution if only because the hardware cannot crash and of course the development cycle will be reduced significantly with ready to roll components.