Few MHz scope frontend?

[Martinn]

In a former post https://www.eevblog.com/forum/projects/usb-logic-analyzerscope-with-sigrok-apprentice-project/ I have been looking for a cheap and simple MSO project, but after many interesting ideas, this came down (due to apprentice level complexity, budget and effort limits) to a USBee AX-pro compatible version. I could simply buy this (e.g. LHT00SU1 clone, see PCB picture here https://www.eevblog.com/forum/projects/usb-logic-analyzerscope-with-sigrok-apprentice-project/msg4943815/#msg4943815, remember volume I am interested in is around 20-50 pcs), however its "front-end" is pretty poor.

So here I am looking for a front-end feeding an 8 bit ADC with 12 MS/s max. sampling rate. I want it isolated (current plan is to use digital isolators for the 8 ADC data and 1 clock lines), in addition we have lots of pulsed signals and little "true" analog, so I'd go for a somewhat higher bandwidth and am not worried about aliasing. 10 MHz sounds adequate. From the voltage range, must is 50 V max. fullscale range, going down to maybe (wish) 5 mV fullscale, which would be a 1:10000 range. Besides AC/DC coupling I'd like an adjustable offset so you could zoom into a 10 mV signal sitting on a 1.5 V baseline.
Unless I find someone who modifies sigrok to control front end parameters (attenuation, coupling, offset) (or do it myself), changing all those settings has to be manual, in its most primitive form by jumpers and a potentiometer for offset. Better of course programmable in case someone finds the time to implement that in sigrok.

Oscilloscope frontends have been discussed here a number of times, although usually for higher bandwiths. Old Tek or Hameg (see here https://cdn.rohde-schwarz.com/hameg-archive/HM205-3_deutsch.pdf on page 37 for a HM205-3 input amplifier schematic) designs are not really helpful as they are designed around custom multi-level cam switches, which are difficult to emulate electronically.

Better starting points seem https://hobby-research.at.ua/NS3/NS_3.0_rev_3.0_.pdf (mentioned somewhere in this forum) or the Hantek 6022BE https://www.eevblog.com/forum/testgear/hantek-6022be-20mhz-usb-dso/msg2554422/#msg2554422 frontend.
Naively I thought "TI makes those nice PGAs, just use one of those"... best I came up with was PGA113 with "scope gains" 1 2 5 10 20 50 100 200, however its 10 MHz x1 bandwitdh drops to 230 kHz at x200.
So I think direction is one or two prescalers (1:100, 1:10) and one or two selectable gain stages (1 up to 50 as shown in the schematic above).  Stanford Research SR560 might also be an inspiration, but this is very low noise and bandwidth 1 MHz only.
Final consideration would be about probe connection - adding a 1/10x passive probe would increase dynamic range "for free", but those I have encountered were crap quality and simply adding a passive probe triples the bulk of the whole setup. I find the tiny size of the Saleae logic 8 really nice - needs about as much space as your mouse. So I'd put the analog input just besides the digital ones on the 0.1" connector for adding "dupont" style mini grabbers. At 10 MHz bandwith and 10 cm cable I think I could get away with that.

Any ideas?

[dobsonr741]

I’m trying to grasp your motivation to build an a
oscilloscope/logic analyzer vs buying it. What I understood so far it’s for employees of a company, 20..50 people or oscilloscopes. Is that right?

[Martinn]

I’m trying to grasp your motivation to build an a
oscilloscope/logic analyzer vs buying it. What I understood so far it’s for employees of a company, 20..50 people or oscilloscopes. Is that right?

Absolutely valid point, but I have replied to that already, for example https://www.eevblog.com/forum/projects/usb-logic-analyzerscope-with-sigrok-apprentice-project/msg4943779/#msg4943779

The origin is a discussion I had with a colleague. The idea was: It would be nice if every workplace, including home office (=x2) had a small saleae logic, plus some spares for disappearing ones. These would be OK for 90% of our measurement jobs (we have enough of full featured MSOs that cover 100%, but often the small Saleae logic is more convenient).
But: The original Saleae logic 8 has disappeared long time ago and is replaced by an army of $8 clones. As professionals, we enjoy the idea of being paid for your work so we are not too enthusiastic about those clones.
So the idea was: Start an apprentice project building a somewhat enhanced USB logic analyzer. On top of our wish list would be a analog scope channel, which is what this thread is about. While a no-go economically based on employee labor cost, I could see this as a good apprentice project. We are always looking for interesting jobs for them, they do a lot of tooling or test setups.

But overall the chances we build that are slim. Still, interesting thoughts... Other people solve Sudokus for fun, why not try to design a 10 MHz frontend?

[dobsonr741]

I agree with the choices, whether it should be Sudoku or front-end design, as a personal preference. However, I find it challenging to reconcile and reach the same decision for a company.

However, if you aim higher than 10MHz frontend it all changes. An example: https://www.bunniestudios.com/blog/?p=3957

[Martinn]

Yes, I should have used the title "Few GHz scope frontend?" 

[mwb1100]

But: The original Saleae logic 8 has disappeared long time ago and is replaced by an army of $8 clones. As professionals, we enjoy the idea of being paid for your work so we are not too enthusiastic about those clones.

As I understand it, the clones (and the original Saleae Logic) are essentially a Cypress SoC dev board.  The real Saleae IP is in the firmware and software.

If you use the  Cypress SoC "clone" with the open source sigrok, you are not using Saleae IP.

That may or may not make you feel more comfortable.  Of course, you'd need to verify that sigrok's software meets your needs.  And of course that doesn't get you the analog channel.

[David Hess]

From the voltage range, must is 50 V max. fullscale range, going down to maybe (wish) 5 mV fullscale, which would be a 1:10000 range. Besides AC/DC coupling I'd like an adjustable offset so you could zoom into a 10 mV signal sitting on a 1.5 V baseline.

With only a 10 MHz bandwidth, 0.5mV per division becomes feasible because lower bandwidth limits noise.

Offset adjustment is feasible however it requires the following stages to gracefully handle overload.

[PCB.Wiz]

Naively I thought "TI makes those nice PGAs, just use one of those"... best I came up with was PGA113 with "scope gains" 1 2 5 10 20 50 100 200, however its 10 MHz x1 bandwitdh drops to 230 kHz at x200.
So I think direction is one or two prescalers (1:100, 1:10) and one or two selectable gain stages (1 up to 50 as shown in the schematic above).  Stanford Research SR560 might also be an inspiration, but this is very low noise and bandwidth 1 MHz only.

Yup, you will need to work backwards from your 10MHz power bandwidth, at the gain you target.

Final consideration would be about probe connection - adding a 1/10x passive probe would increase dynamic range "for free", but those I have encountered were crap quality and simply adding a passive probe triples the bulk of the whole setup. I find the tiny size of the Saleae logic 8 really nice - needs about as much space as your mouse. So I'd put the analog input just besides the digital ones on the 0.1" connector for adding "dupont" style mini grabbers. At 10 MHz bandwith and 10 cm cable I think I could get away with that.

You need to be targeting 1Mohm input, to allow for standard 10:1 probes.
That likely means a CMOS opamp.

Rail-Rail I/O is 'nice to have' but with gain already there, that's not vital.
I cannot find any fast-enough+CMOS+RRIO parts,  but if you relax to RRO, then parts like LTC6268/LTC6269 look in the ballpark.
Of course, those parts are not 'LM358 prices'  and will need care in layout.

The ADA4891 series have worse offset, but are cheaper, so it becomes a decision of where you want to be on the price curve.
I think the SOT23 parts are generic pinouts, so you could build some using each and compare.

Addit: maybe another one to try ?  https://www.lcsc.com/product-detail/Operational-Amplifier_Gainsil-GS8091-TR_C157724.html

[rhb]

A  TL08x JFET opamp will give you 3 MHz at any impedance you want with proper matching.  Use a digital pot to set the gain with another one following the input voltage follower.  Add  an STM32F429 and you have 3 channels at 1.2 MHz or 1 at 3.6 MHz Nyquist and a complete touch screen DSO for less than $50 in parts. 

However, you  mentioned "analog scope" which has me a bit confused. 

Reg

[Martinn]

That may or may not make you feel more comfortable.  Of course, you'd need to verify that sigrok's software meets your needs.  And of course that doesn't get you the analog channel.

The LHT00SU1 is supported by PulseView (see screenshot here https://www.eevblog.com/forum/projects/usb-logic-analyzerscope-with-sigrok-apprentice-project/msg4943815/#msg4943815), although certainly not in the league of the Picoscope software. The idea here is to use this exact software as starting point.

A  TL08x JFET opamp will give you 3 MHz at any impedance you want with proper matching.  Use a digital pot to set the gain with another one following the input voltage follower.  Add  an STM32F429 and you have 3 channels at 1.2 MHz or 1 at 3.6 MHz Nyquist and a complete touch screen DSO for less than $50 in parts. 

No point messing with a crap 3" display when you have 30" in front of you (so it has to be a PC scope). And as I don't see anyone volunteering (for now) writing a custom LA/scope windows software, Sigrok Pulseview it is (other suggestions?) and specifically the https://sigrok.org/wiki/HT_USBee-AxPro AXPro variant.

Offset adjustment is feasible however it requires the following stages to gracefully handle overload.

Good point to have in mind, thanks. I have to figure out where to inject the offset in order to get the best range. Most likely will need coarse/fine or 10T pots. BTW due to I think jonpaul (or was it you) mentioning the AM 502 differential amplifier repeatedly, I now have one in my rack. It would tick most of the requirements: AC/DC/GND input coupling (even differential), 1:100 prescaler, 1:1000 step gain/attenuator, very wide offset adjust with concentric coarse fine knobs... But let's stay on the ground.

You need to be targeting 1Mohm input, to allow for standard 10:1 probes.
That likely means a CMOS opamp.

Rail-Rail I/O is 'nice to have' but with gain already there, that's not vital.
I cannot find any fast-enough+CMOS+RRIO parts,  but if you relax to RRO, then parts like LTC6268/LTC6269 look in the ballpark.
Of course, those parts are not 'LM358 prices'  and will need care in layout.

The ADA4891 series have worse offset, but are cheaper, so it becomes a decision of where you want to be on the price curve.

Addit: maybe another one to try ?  https://www.lcsc.com/product-detail/Operational-Amplifier_Gainsil-GS8091-TR_C157724.html

I have not yet considered possible amplifier choices. As there seem no usable PGAs, I need to figure out the attenuator/gain stages first and then work back from the GBW. Not sure it needs to be CMOS - there is no precision involved - 8 bit ADC only and offset adjust knobs.
AD8065 seems popular (see schematics in first post, Hantek 6022BE for example) but lacks GBW for amplification.
Interesting usage in second schematic of https://www.analog.com/media/en/technical-documentation/data-sheets/AD8129_8130.pdf for gain and offset adjust.

Gainsil: I have used a GS8333 in one design - three channels were fine, one behaved strangely... For now, I'll stick with ADI/TI etc. for nontrivial stuff.

[PCB.Wiz]

Not sure it needs to be CMOS - there is no precision involved - 8 bit ADC only and offset adjust knobs.

CMOS is because you need to source from 1 Meg, and so bipolar bias currents are too large, and would give offset errors.
Fortunately, there are CMOS choices.
A couple of stages may be needed to get the GBW targets.

[Martinn]

CMOS is because you need to source from 1 Meg, and so bipolar bias currents are too large, and would give offset errors.

As I wrote earlier one feature I'd like is a wide offset adjustment range - like +-10 V in a 0.1 V range. With that, static offset errors from input bias currents seem irrelevant, unless it saturates the input. Either way AD8065 seems fine.

[Nominal Animal]

As I understand it, the clones (and the original Saleae Logic) are essentially a Cypress SoC dev board.  The real Saleae IP is in the firmware and software.

If you use the  Cypress SoC "clone" with the open source sigrok, you are not using Saleae IP.

Can confirm.  It is such a direct match that you can use the same Sigrok fx2lafw firmware on Cypress dev boards (like CY7C68013A).
Just look at the original Saleae Logic board from 2010, and compare to any CY7C68013A board, including Cypress original dev boards.  Board shape and input pin protection varies, but that's about it.

The firmware is loaded on Pulseview startup, and is the only thing running on the board (other than what Cypress has built-in to the chip).  Even if the board has code in Flash/EEPROM, that code is not used.

[David Hess]

CMOS is because you need to source from 1 Meg, and so bipolar bias currents are too large, and would give offset errors.

As I wrote earlier one feature I'd like is a wide offset adjustment range - like +-10 V in a 0.1 V range. With that, static offset errors from input bias currents seem irrelevant, unless it saturates the input. Either way AD8065 seems fine.

The higher input current noise associated with a higher input bias current will dominate the input noise when it is applied to the input protection network.  Bipolar parts with suitably low input bias current to support a 1 megohm input do exist, however they have marginal bandwidth and slew rate for a 10 MHz input.

There is no reason not to use a faster CMOS or JFET part for the input.  If you are interested in low noise performance, then there are some suitable low noise JFET parts which can be used for the input buffer.  After the input buffer, input bias current becomes irrelevant and any technology can be used.

Also for the input buffer, and all later stages as the signal level increases, slew rate is very important.

[Alex Eisenhut]

I don't know but I'd suggest checking out the Tektronix books from the 1960s about it.
https://www.davmar.org/concepts.html
Read all of them.

[Martinn]

OK, first try. As this is honestly for fun only and there are almost no clear requirements, I struggled a bit about what to actually build.
Main data: 10 MHz BW, 0.5 mV/div - 20 V/div sensitivity, 1 MOhm input, driving 8 bit ADC with 2 Vss input (means 500x gain at 0.5 mV/div or 4 mV FS). Wide offset capability, settable bandwidth down to say 10 kHz.
Here's where I'm at currently, feedback welcome:
Input attenuators (1/10/100/1000)  stripped down, hopefully sufficient for 10 MHz. No 10:1 passive probe support (as this would require adjustable attenuator input capacitances - trimmers are $3 actually!). As the frontend FET amp has sufficient GBW, I decided to make it 2x gain and add the first coarse offset shift on top (not sure about the bias noise introduced by LM358 - not specified). Noise at output is 14 nV/rtHz or about 60 uV over a 20 MHz bandwith. With full 250x gain this gives 2 LSB noise RMS (maybe 6 LSB p-p), so for full 8 bit either reduced bandwith or gain is necessary.
What's still missing: The remaining 250x gain with selectable 1/2/4 divider and selectable x10 gain. So it could be: 1/2/4 divider, 25x gain, selectable 10x gain. On top: Fine offset adjust somewhere and bandwitdh limit (say 1 MHz/100 kHz/10 kHz).
Questions: Should I for the remaining part use +-5 V opamps or just go +5 V single supply? ADC input is 0.6-2.6 V.
How to implement the 1/2/4 +25x gain? Either 25x amplifier with multiplexed resistor divider or selectable opamp gain via feedback resistors?
Should I attempt 25x gain in one stage (needs 500 MHz GBW probably) or better two stages?
Bandwidth limiter: Three R/C switched by a 4052?
Current idea: ADA4891: 230 MHz, 5V, 10 nV/rtHz. 25x split in two sections, 10x needs also two sections, four opamps total. Not sure about that.