Right, current flow counts. Well, what current is flowing through the inductor?
It's a ramp. Or a rampy sort of thing, anyway. Basically, the trace inductance adds in series with the inductor's -ance, and acts as a voltage divider to the SW waveform. So you still get square waves, but much less than anything coupling directly with the highlighted current loops.
It's not strictly true that loops should be minimal. Monolithic regulators don't leave much choice in design, but doing it with an external-switch type, or a larger inverter of your own design (where it's worth adding the snubbers and such for both EMI and efficiency reasons), it's important.
BTW, app notes and examples and such, are only as good as the people (lower tier engineers, technicians or interns?) who make them. They are rarely good examples of design.
My favorite example to point and laugh at is,
http://www.ti.com/lit/an/slpa010/slpa010.pdf which basically only manages to touch the issue, and shows no understanding of the underlying problem. Namely: since it's demonstrably inconvenient (wasteful R+Cs) or impossible (the ringing never goes away in any of their examples) to do it "following general advice", that advice must be wrong.
Since it can't be dealt with in parallel, loop inductance must be damped in series: by opening up the inductive loop and damping that inductance (usually with an R || L, or an RCD snubber). This begs the question, how much L and C is best, if not zero? The answer is, the product should be similar to, or smaller than, the switching speed (and must be less than 1/20th of the cycle time, give or take -- otherwise too much of the switching cycle is spent circulating reactive power, usually wasting it in dampers or snubbers and edge transitions), and the ratio Z = sqrt(L/C) (L being parasitic loop inductance, and C being Coss of the transistors) equal to the peak-to-peak voltage and current output from the inverter.
Tim