Estimate JFET pn junction area from datasheet or spice values

[matthuszagh]

I'm designing a circuit that may expose JFETs to very brief high power pulses. To ensure reliability, I'd like a way of modeling failure rates as a function of power and pulse duration. I'll test everything, of course, but I'd like to start with a rough theoretical model to restrict the testing. This paper (https://ieeexplore.ieee.org/abstract/document/4325054) provides a simple model of failure for power/time combinations. It only requires pn junction area as an input.

I have not been able to find junction area information in datasheets. And I don't think it's embedded in the spice models either, though I could be wrong. Is there a way of estimating this from provided values, without simply asking the manufacturer? For instance, maybe it can be estimated from input capacitance values?

Also, if anyone knows of resources (more recent perhaps) on semiconductor failure modelling from very short (sub microsecond), high power pulses I'd be very interested to know of them.

[Kleinstein]

The classic Fairchild AD-6609 has drawings with dimensions for the classic US JFET types.  The gate capacitance should be a reasonable good proxy for the area. However the DS values are sometimed given for different conditions - so not all numbers are directly comparable  (capacitance with 0 voltge is quite different than the capacitance at -5 V).

[matthuszagh]

The classic Fairchild AD-6609 has drawings with dimensions for the classic US JFET types.  The gate capacitance should be a reasonable good proxy for the area. However the DS values are sometimed given for different conditions - so not all numbers are directly comparable  (capacitance with 0 voltge is quite different than the capacitance at -5 V).

Oh this is great, thanks! FYI for anyone else coming across this I think that should be "AN-6609".