So I leave it there in case someone may be interested in the future. I increased the values for R4 (left it as in AN21) and R6 to make the parallel connection more similar to the original 12k value. For R5, I increased to 600k to take some distance from R6, and has to be tweaked either up or down to adjust the offset sensitivity. In any case, one could tweak a bit also the integrator cap C1 to slow it down if necessary, but I think that overall this is a good starting point, and the rest are adjustments.
EDIT: Also attached a tweaked inverting configuration after trying to perform myself something some noise calculations with LTSpice. C1 helped me at lower frequency, and one can also tweak C2 in case wants a different BW (obviously, this affects the overall output noise level -because of the the different BW-, but the density itself doesn't change). Many thanks to user magic for helping me with this.
EDIT 2: As a final afterthought, one can also think of splitting the system into cascading 10x (which also seems nicer for a simple amplifier project), which overall lowers the noise a little bit further. There's also a rough noise analysis done by myself. For 10x, I made a test trying to increase the resistors to 10k/100k for an higher input impedance, but obviously one gets lower noise with 1k/10k divider, with integrator resistor still at 10k. After further trials, around 3k/30k seems a good upper limit.
Finally, mind that this simulation still ignores the NE5532. Results are below