Driving lots of TFT SPI screens at high speed

[DavidMenting]

Thanks for all your thoughts so far. I'm going for the modular approach – I sent these puppies in for manufacturing today:


The pads at the top connect to the 2.2" TFT. I've added a termination resistor on the SCL and SDI line and some power supply filtering. Now it's time wait for the boards to come in and to focus on the Raspberry Pi's end

[jmole]

those termination resistors (ideally) need a much lower impedance path to ground. why not add a via between the resistors to the ground plane?

Thanks for all your thoughts so far. I'm going for the modular approach – I sent these puppies in for manufacturing today:


The pads at the top connect to the 2.2" TFT. I've added a termination resistor on the SCL and SDI line and some power supply filtering. Now it's time wait for the boards to come in and to focus on the Raspberry Pi's end

[DavidMenting]

those termination resistors (ideally) need a much lower impedance path to ground. why not add a via between the resistors to the ground plane?

Good one. I'll have to add that to a second revision, though.

[mikeselectricstuff]

those termination resistors (ideally) need a much lower impedance path to ground. why not add a via between the resistors to the ground plane?

It's a resistor. Any additional track resistance will just add a tiny fraction more resistance.

[jmole]

those termination resistors (ideally) need a much lower impedance path to ground. why not add a via between the resistors to the ground plane?

It's a resistor. Any additional track resistance will just add a tiny fraction more resistance.

you've got more expertise than I on this, but it seems like the impedance to ground is what matters, not the resistance. It's a short trace, so the stray inductance there is likely pretty negligible, but I'd consider it good practice to terminate the ends of the resistor as close to the ground plane as possible. Seems especially important if you're doing single-ended termination without a resistor at the source, since the current being driven is much higher.

[DanielS]

It's a resistor. Any additional track resistance will just add a tiny fraction more resistance.

And a few extra nH of inductance.

To reduce the amount of power wasted in termination resistors when the I2C bus is idle, I would use RC termination instead.

[DavidMenting]

It's a resistor. Any additional track resistance will just add a tiny fraction more resistance.

And a few extra nH of inductance.

To reduce the amount of power wasted in termination resistors when the I2C bus is idle, I would use RC termination instead.

Would that just be a matter of putting a capacitor (100pF?) in series with the resistor?

[DavidMenting]

Okay, I've taken the plunge and have gone for the Lattice FPGA/CPLD option. Luckily, I found someone who wanted to get me started with the tools and the basics of it.

and...

It's great!  Thanks for the suggestion, Mike.

The breakout boards have come in and seem to work perfectly. Here is a setup with six screens hooked up.



The Lattice MachXO board splits the CLK, MOSI, RESET and D/C signals using the following Verilog code:

Code: [Select]

assign out_clk[7:0]   = {8{spi_clk}} ;
assign out_sdi[7:0]   = {8{spi_mosi}} ;
assign out_dc[7:0]    = {8{tft_dc}} ;
assign out_res[7:0]   = {8{tft_reset}} ;
I'm still working on the CS logic that switches to a different screen once an SPI transfer is completed.