DDS generator output amplifier

[Dago]

I'm making a DDS based function generator (sine and squarewave for something like 50Hz-8MHz). I have the DDS part working and I'm working on the output amplifier section (since the DDS chip outputs around 200mV p-p). The first output amp version I built was actually (unknowingly at the time) based on Dave's schematic ( http://alternatezone.com/electronics/images/DDSFreqGenSchematic.gif ) I used a AD847 for the op-amp but it was way too slow (and I suspect the EL2044/LM6361 will be as well) and got like -20dB attenuation @ 8MHz (due to opamp bandwidth product limit). Well I made a new version with way faster LT1225 op-amps and used two amplifying stages to get around the bandwidth limit problem (then only thing really limiting is the slew rate and these opamps have a pretty good slew rate). Well it's working WAY better but uhh... the problem this time is that the gain actually goes UP with frequency which is uhh sort of baffling

Atm. I have two non-inverting amplifying stages with gain = 5 back-to-back, with a 33k feedback resistor and a 8,2k resistor going to ground from the minus input. Pretty much the same schematic as Dave's. What I'd essentially want is AROUND (its not THAT critical, +-20% is fine with me) 1V p-p from the first amplifying stage and 5V from the second one (I'm going to use an analog multiplexer to select which voltage I want on the output).

Here's a capture of the first stage at 100kHz and everything is working as calculated (Yellow or Vpp(1) is the input and blue or Vpp(2) is the output):



Then at 8MHz gain goes over 8:



Anybody got any ideas whats happening and what can I do to get rid of it? Only thing I can think of right now is that I'm hitting some resonance and getting extra gain due to that.

Edit: Here's my PCB layout, the two SO-8 up from the lower left corner are the two op-amps: http://www.dgkelectronics.com/storage/electronics/function_generator/dds_output_layout.png Rest of the stuff isn't even soldered in yet.

[Dago]

Found it Always remember to read the datasheet: "Design Note 50. Feedback resistor values greater than 5k are not recommended because a pole is formed with the input capacitance which can cause peaking. If feedback resistors greater than 5k are used, a parallel capacitor of 5pF to 10pF should be used to cancel the input."

I reduced the resistor values to 4,7k and 1k and now I get ~1.2V first stage @ 100kHz, 920mV @ 8MHz and second stage 6,9V @ 100kHz, ~5.3V @ 8MHz.

[Dago]

Hmm, weird. I attached a NPN + PNP (BC639 + BC640) totem-pole to the opamp output (bases fed through a 470ohm resistor) and the NPN collector is attached to a 15V supply and the PNP collector is attached to the ground, but its not working correctly. I just get around 3,5V out from the emitters (output varies with frequency a bit but I tried everything from 100kHz to 8MHz). I'm 100% sure the transistors are fine and are wired correctly. What could be wrong?

[Dago]

Finished it, heres a page about it: http://www.dgkelectronics.com/page.cgi?page=dds_gen