Do you verify the netlist before PCB layout?

[zapta]

When you are done with the schema and ready to start the board layout, do you verify the netlist? I mean manually over the netlist and verifying each net and node?

[Rerouter]

kicad has an option to cleanup unconnected tracks in its schema package, equally DRC will point out any unconnected pads (you have to specify "do not connect" to make it not flag (modifying pins to the right type for DRC is helpful here)

with these tools i am confident that i wont need to verify line by line, and i use the schematic not just the net-list while laying out (to keep in mind what needs to be kept close and low noise etc) which is a second chance for me to pick up any issues in my schematic.

[c4757p]

If the netlist isn't a perfect listing of what touches what in the schematic, there's a bug report to be filed...

[zapta]

If the netlist isn't a perfect listing of what touches what in the schematic, there's a bug report to be filed...

You cannot derive the correct netlist just by looking at a schematic.

In eagle for example, hidden shared names can make a connection and misplaced network names can look as connections but are not.

[rfbroadband]

Usually you run what is called DRC (design rule check). The following pics provide an idea of all the things you should verify and check. All the CAD tools are slightly different, but I assume every schematic capture has the ability to run these checks automatically.


When you are done, you better have a perfectly clean DRC error list like the one below...

Date and Time : 02/04/14 22:22:16

--------------------------------------------------
Checking Schematic: SCHEMATIC VBus Mon
--------------------------------------------------
Checking Electrical Rules

Checking For Single Node Nets

Checking For Unconnected Bus Nets

Checking Off-Page Connections

Checking Pin to Port Connections

Checking Physical Rules


Checking Pins and Pin Connections

--------------------------------------------------
Checking Schematic: SCHEMATIC Demo Design
--------------------------------------------------

INFO(ORCAP-2242): Checking Incorrect Pin Group Assignment

Report for Invalid References

Report for Duplicate References

--------------------------------------------------
Checking Entire Design: Demo Design
--------------------------------------------------

Checking Power Pin Visibility 

Checking Normal Convert View Sync 
INFO(ORCAP-36105): Checking Missing Pin Numbers 

Checking Device with Zero pins 
INFO(ORCAP-36101): Checking Missing PCB Footprint Property 

Checking Name Property for Hierarchical Instances 

INFO(ORCAP-2211): Check High Speed Properties Syntax

INFO(ORCAP-2212): Check Power Ground Mismatch

Reporting Unused Refdes in multiple part packages
Part                          Quantity                          Reference
-----------------------------------------------------------------------------------------

[uoficowboy]

If I'm not doing the layout, I definitely will check the netlist. If I'm doing the layout myself, it's less important but I may still check it.

It's great for catching things like slightly misnamed nets (ie SPI_SCK and SPI-SCK).

[AlfBaz]

Usually you run what is called DRC (design rule check). The following pics provide an idea of all the things you should verify and check. All the CAD tools are slightly different, but I assume every schematic capture has the ability to run these checks automatically.


When you are done, you better have a perfectly clean DRC error list like the one below...

...and here I was wondering why I never get errors 

[HackedFridgeMagnet]

...and here I was wondering why I never get errors 

it seems like you're just saving your errors up for a rainy day.

[rfbroadband]

Usually you run what is called DRC (design rule check). The following pics provide an idea of all the things you should verify and check. All the CAD tools are slightly different, but I assume every schematic capture has the ability to run these checks automatically.


When you are done, you better have a perfectly clean DRC error list like the one below...

...and here I was wondering why I never get errors 

:-) which tool is that ?

[AlfBaz]

Altium

[Mechatrommer]

apart from the mentioned, diptrace way of highlighting all lines in the net realtime while in edit/schema/pcb mode is pretty handy, not some arbitrary disconnect of lines union that should not in the care of ee engineers.

[free_electron]

Altium

that is the default option of you use a pirated copy

Altiums checker is very good. in all my board designs i have never had problems with missing connections. If the schematic is correct the board is correct.

[AlfBaz]

Altium

that is the default option of you use a pirated copy

Get bent free... It was a joke, hence the winky smiley face

[nctnico]

If the netlist isn't a perfect listing of what touches what in the schematic, there's a bug report to be filed...

You cannot derive the correct netlist just by looking at a schematic.

In eagle for example, hidden shared names can make a connection and misplaced network names can look as connections but are not.

That sounds more like a problem in the CAD software / schematic than the netlist. I mostly use Orcad and some old libraries have hidden power pins. I usually change these components to have all pins visible.

During layout I usually change the colors of the ratsnests for certain nets like power, ground or nets with high voltages/large currents. That also gives some insight in how everything is connected.

[andyturk]

Hey rf, your last screen grab of the ERC matrix looks like it's flagging an error when you connect an "input port" to an "output".

Why is that an error?

[rfbroadband]

Hey rf, your last screen grab of the ERC matrix looks like it's flagging an error when you connect an "input port" to an "output".

Why is that an error?

I don't recall why this flag was set in this particular case.

[free_electron]

That sounds more like a problem in the CAD software / schematic than the netlist. I mostly use Orcad and some old libraries have hidden power pins. I usually change these components to have all pins visible.

bingo. hidden pins should be made illegal and fined !

[c4757p]

bingo. hidden pins should be made illegal and fined !

Fined? I say it's time to bring back public corporal punishment...

[free_electron]

bingo. hidden pins should be made illegal and fined !

Fined? I say it's time to bring back public corporal punishment...

YAY . stocks, tar and feathers.

[TerraHertz]

Back when I was still doing PCBs, (Protel, Orcad) I'd generally print a copy of the schematic, and the netlist, and use a hi-lighter to make damn sure they matched. Every now and then there'd be an error. Bad parts in the library, mistyped net names, etc.

But the really useful sanity check was later, after the board layout was done. I'd delete the netlist in the CAD program, leaving just the copper layout and components. Then tell it to rebuild the netlist from the copper. I think it was Protel that had a feature to do that, and then compare the resulting netlist to the original one.

*That* tended to find some surprising errors.
Thanks to doing  that, I had pretty good luck with boards working first time.

In general, if you're doing commercial PCB design and you find yourself wondering whether to put in a few hours tedious work with a hilighter, or skip that and just go ahead and send out some gerber files that will take weeks of turnaround and cost a pile of cash, fingers crossed they are OK, then you shouldn't be doing commercial PCB design.
It's also good to have someone else review both your schematic and PCB layout.

[nctnico]

What helps is to turn everything off except the rats nest. That way you can see whether every net has been connected. Most layout software has a feature to show the number of unconnected nets. In some packages (for example Orcad layout) this doesn't work quite well.

[peter.mitchell]

Altium

that is the default option of you use a pirated copy

Altiums checker is very good. in all my board designs i have never had problems with missing connections. If the schematic is correct the board is correct.

Get bent free... It was a joke, hence the winky smiley face

I'm not sure what is implied here?
It appears to me that he has disabled all warnings for all violations, for what appears to be pure laziness.

What does this have to do with Piracy? Do the people who provide the pirated software set the settings like this in hopes to spite you?

I do agree about the checker though, it is very good, I have had no issues ever aside from those related to user error. Even vast updates to schematics from changing the PCB and pushing the change to the schematic has been trouble free (I have encountered errors/issues with other programs here).

bingo. hidden pins should be made illegal and fined !

Fined? I say it's time to bring back public corporal punishment...

YAY . stocks, tar and feathers.

Agreed, it was one of the first things I learned when looking at schematics, this is a brief summary of a conversation I had with a colleague whom I tended to avoid afterwards.
Q "Where are the supply pins on that 7400 series?"
A "Oh, they're taken care of, don't worry."
Q "What the heck do you mean taken care of, don't worry? What if i want to see what it's connected to, or make sure it IS connected or change where it's connected? Why does it have to be hidden? If it is too annoying to have on each part of the chip (assuming multi part component EG, IC1A, IC1B, IC1C, IC1D) can't you at least have it as another part of the component off on a different page or somewhere more discreet?"
A "Nah, why would you want to do that anyway?"

I am quite trusting of the checker in Altium, but that doesn't mean I don't manually check as much as I can before I send out the gerbers.
Usually i print the gerbers out on A3 transparencies, then join the dots with different coloured dry erase markers.

[Gribo]

Depends on the design. On a 4 or 2 layer cheap board, I usually don't bother. On an 8 layer, limited production run, I check every net. My method is the same as mentioned above, with transparencies, markers, and another engineer for double checks.

[peter.mitchell]

Depends on the design. On a 4 or 2 layer cheap board, I usually don't bother. On an 8 layer, limited production run, I check every net. My method is the same as mentioned above, with transparencies, markers, and another engineer for double checks.

I'm pretty pedantic on ALL boards, time is money, and if it takes me a few hours to triple check a board, vs a week and a bunch of money for a re-spin, it's worth it.

[AlfBaz]

I'm not sure what is implied here?
It appears to me that he has disabled all warnings for all violations, for what appears to be pure laziness.

What does this have to do with Piracy? Do the people who provide the pirated software set the settings like this in hopes to spite you?

Emoticons just don't seem to be big enough for some!

I went through and cycled them all to green just to just to take a screen capture for a dumb "dad joke" post, hence the  emoticon.
Obviously I pressed cancel on the DRC dialog after doing so. If anybody was that lazy, surely they'd just ignore the DRC markers

Then it seemed to be implied that I had pirated software and I took offense