This simpler version also has 3us of short circuit current overshoot.
Overshoot where? On the CS resistor, or on the load? To understand the importance of the question, see attachments:
-Green: output load
-Blue: current sensing resistor
The first(Load&CS_W_RC(1+4.7).png) has an RC snubber over the output, 1µF+4.7Ω, exactly like in your drawing; current within 10% the target(1.5A) shortly after the 70µs mark.
The second(Load&CS_W_RC(082+22).png) RC snubber is 82nF+22Ω; current within 10% the target(1.5A) around the 15µs mark.
The third(Load&CS_WO_RC.png)has no RC snubber over the output; current within 10% the target(1.5A) around the 12µs mark, but with ringing extending up to the 40µs mark.
Note: the CS resistor is in series with the main supply, exactly like in your drawing; on my previous screenshots were in series with the load.
It takes around 5µs
1 for the CC circuit to take over the bypass transistor control, that's the spike around the 11µs mark.
Simulation command: .tran 0 4.5m 4.395m startup ; PULSE(1 2 4.4m 1u 1u 90u).
Schematics: I intend to release it soon, in public domain; since is niche of the niche, not worth trying to monetize IMNHO, even if it would be patentable.
15µs is the time required to discharge the compensation capacitors in the CV section.