Here is the first proposal of pin mappings for backplane that I'd like to use to connect more modules within a single chassis.
The foundation of everything is a digital control based on the principle of a single processor (
master) module that would take care of more peripheral (
slave) modules. Although a good specification should be "architectural agnostic" this one is, as you will see, inspired or suggestive of using a XMOS parallel processing MCU, but that does not mean it could not be usable with any other MCU family.
Power lines3.3 V is used as the main power supply for peripheral modules. It is also backed up with
+3.3VAUX and
Vbat outputs that should be used for standby mode. The additional power supplies are
+5V,
+12V and
-12V. In addition, several pins for
GND are provided. There is currently no PE (Protective Earth) that may need to be added to avoid providing additional wiring out of the modules if necessary. A possible advantage of using the separate wire is higher current rating as perhaps better/easier arrangement of the star structure.
The power supply section can be placed on the processor module itself or brought from the outside.
System signalsIt is envisaged to bring a "master clock" signal of 100 MHz to all peripheral modules. Because of the speed, it might be mandatory to be provided over differential lines. For this reason, I predicted two pins for it:
MASTER_CLK+ and
MASTER_CLK-. It should not be confused with the SPI clock signal, since it is provided through
SCLK1 to
SCLK7 pins.
#RESET is the next important system signal generated by a reset generator/power supervisor on processor module #0.
Optional, or maybe better to put them as mandatory from the beginning, are five signals for JTAG debugging (TDI, TDO, TCK, TMS, #TRST).
Communication between modulesThe basic communication between processor and peripheral modules is SPI where for each module a separate SPI channel is dedicated to enable parallel operation, assuming that the CPU/MCU is capable of doing something like this, as in case of the mentioned XMOS xCORE. If other MCU is to be used then it will be necessary on the processor module to merge multiple SPI channels to what the MCU (at least on the physical level or pins) offers separately. Plenty of MCUs have several SPI channels, the other thing is that there is still just one processor core that have to deal sequentially and not in parallel with the connected peripherals.
SPI channels have three signals SCLK, MOSI and MISO. The question remains what about CS (Chip Select) which is also needed if we have more than one SPI device on the same SPI channel. For this purpose, pins
#CS1 to
#CS7 are foreseen. Now, this would mean that it is possible to have only one SPI device per module. However, with simple trick it become possible to address x peripherals. We have to deploy a SIPO register such as
'595 for addressing up to 8 peripherals, of more if they are daisy-chained (16, 24, etc). Of course, the greater the number of SPI peripherals on the module, the access time could be slower. However, since the '595 has access speed that largely exceed the usual SPI speeds, it would in this way greatly or wholly neutralize the delay of such addressing. E.g. if the SPI device with max. speed of 4 MHz is used, and there are up to 8 of them, if the '595 is accessed with more than 30 MHz first, and then proceeds with SPI communication at 4 MHz, the end result should be the same as if '595 is not present at all. Furthermore, I assumed that we could have a very fast SPI devices on the first two slots (closest to the MCU!) and want them to access with, say 20 MHz. In that case, the '595 signaling could also go over 100 MHz. For this reason it is envisaged that CS1 and CS2 can be differential, so we have
#CS1 Diff+,
#CS1 Diff-,
CS2 Diff+ and
#CS2 Diff-.
Additionally, for slower functions, I2C can be used, which is shared between all peripheral modules (slot #1 to #7).
Finally, if using xCORE, they allow multiple MCUs to be interconnected for e.g. more processing power and I/O lines. This means that main processor resources are no longer necessary resides on slot #0 only, but may be on other slots, too. For such a connection, a
2-wire xCONNECT bus is used, which is slower than a
5-wire variant but consumes fewer pins on both MCUs and connectors (4 instead of 10, or 8 instead of 20 if differential). xCONNECT would be theoretically (and probably practically as advertised by XMOS) used for fast serial communication that should be at least 10 times faster than the usual SPI.
The processor module has an xCONNECT channel that can be used to connect to the remaining modules, but also to connect to another chassis that will have its own processor module and associated peripheral modules.
Triggers and analogue switchesFor the purpose of synchronizing activities between multiple peripheral modules, trigger inputs and outputs are used. Star topology is implemented, i.e. all inputs and outputs are terminated at one end on the processor module. The MCU is therefore in charge of waiting for the trigger (on inputs) and sending the trigger to one or more modules. In the case of a xCORE MCU with a predictable resolution of less than 10 ns, a precise synchronization of multiple modules can be expected.
In addition, I took from the VXI specification the use of cross-point switching that allows the redirection of (analog) signals from x to y module. Depending on the speed required, there are chips that do this for decent price in range from 45 (MT8808) to 300 MHz (ADG2188).
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Below (and in attached PDF) is shown the pin mappings of the #0 connector that has 96 pins (3x32) and other 48-pin (3x16) connectors/slots. The connector suggestion is at the bottom of the text.
As usual, your comments and suggestions are very welcome
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