DGD05473 Gate driver questions.

[drakejest]

I would like to use the DGD05473 to drive a P channel MOSFET SI4143DY.



The gate driver is for high and low side, but im not going to use the low side. Will that be fine?

How much current will the gate driver consumes on my 3v3 supply? the 3v3 is from a 250mA LDO so i want to make sure i wont exceed that. The datasheet mentions

VCC Operating Supply Current ICCOP — 7.3mA

but it this the value the chip will be consuming?

What is the function of the bootstrap ? why does it need to be connected to both mosfets drain ? Is the capacitor really needed between Vb and Vs i could not find a recommended value for it in the datasheet?

I assume that a "HIGH" signal on the high side input pin (HIN) would result on the high side mosfet to being ON. Am i correct? its not like a typical driver where the controls are inverted for the high side PMOS




Thanks in advance 

[T3sl4co1l]

MOSFET drive is with respect to the source.  Hence why you see "Vgs" all over the datasheet.  You've wired the driver to the drain, which, isn't going to work very well I'm afraid.

Also unclear why you're using an N-ch bootstrap type driver with a P-ch transistor.  P-ch is everything upside down, flip all the signs, that's it.  Whereas N-ch needs Vgs > Vgs(th) to turn on, P-ch needs Vgs < Vgs(th) (and threshold is -2.5 to -1V in this case).  But your driver only supplies positive Vgs.  So I'm not sure how you intend to use it successfully here.

Mind, even if you tie source to Vs (the driver's supply reference), it's still wrong under certain conditions -- most importantly undervoltage (UV on the block diagram), which turns off the gate when insufficient supply voltage is available.

Which, hmm... that's gotta be a typo.  Notice how they have "UV" going to an OR gate, to R (reset).  Presumably, UV going true, means insufficient voltage is available.  Reset means, well, reset the Q output (goes false / low).  But they show Q going to a complementary pair of MOSFETs, an inverter.  So they're showing the output as default high.  Which I'm sure wasn't intended and they actually meant a noninverting gate driver output, not the two-transistor inverter.

On the other hand, they also don't provide a truth table; the "UV" function is insufficiently documented.  Maybe it really does go high when disabled?  That would certainly be critical information when using N-ch MOSFETs!

Regarding supply current, read the conditions.  They give a shutdown current, quiescent current, and operating current.  The first two are static, EN = 0 or 1.  The last is for a 500kHz switching frequency into a 1nF load, in other words a 12nC equivalent gate charge (Q = V*C, and Vcc = 12V is given).

If the transistor is changed to N-ch, a problem still remains.

The bootstrap supply, is dubious without a pair of transistors switching alternately like in an SMPS application where these drivers are typically used.  You are depending on load current to pull Vs down towards GND, and thus charge Vb through the internal diode.  You cannot run continuous output-high (100% duty cycle), because the high side supply will eventually bleed through its charge, until it hits UV and forces itself off briefly.  Preferably you do this manually rather than waiting for it, so as to maintain adequate Vgs(on).

Alternately, a charge pump or isolated supply can be added, to supply current to the high side continuously.


Also, this application sounds awfully familiar?.. Aha, yeah, here it is.  I notice you didn't add a reply to this comment:
https://www.eevblog.com/forum/projects/is-it-okay-to-use-an-ldo-at-lower-or-the-same-as-its-rated-output-voltage/msg3593544/#msg3593544
but also you seem to have ignored their advice... it is precisely what you need for a P-ch MOSFET, or various improvements for PWM capability.

Or move the load to the +V side (low side switched), so a N-ch is needed and only a regular (non-bootstrap) driver.

Tim

[drakejest]

Also, this application sounds awfully familiar?.. Aha, yeah, here it is.  I notice you didn't add a reply to this comment:
https://www.eevblog.com/forum/projects/is-it-okay-to-use-an-ldo-at-lower-or-the-same-as-its-rated-output-voltage/msg3593544/#msg3593544
but also you seem to have ignored their advice... it is precisely what you need for a P-ch MOSFET, or various improvements for PWM capability.

I have since abandoned that idea, i have just decided to just get a mosfet that has a gate source voltage rating of higher than the higest voltage that will be applied. So i can just use the source voltage and some sort of totem pole circuit to push and pull on the gate.

It was a good thing that i have asked, there are a lot that i did not notice on this driver, i did not even notice that the high side mosfet was a nchannel not a pchannel.

Or move the load to the +V side (low side switched), so a N-ch is needed and only a regular (non-bootstrap) driver.

As stupid as might this sound, but i really want to use a PMOS just because it is something i have not tried doing yet. My application is just driving a led strip so it would not really matter if i use a PMOS high side switch (i think)


looks like i have to scratch this idea too, and if i cant find a driver then, i guess i will have to attempt to make one myself  . You might see me again asking if my attempt at making a driver is correct 

Thanks for the help!