AD9106 dds chip power supply connections (internal LDO purpose????)

[SArepairman]

I have been really confused about this one for a while.

http://www.analog.com/static/imported-files/data_sheets/AD9106.pdf'

This chip has three built in regulators. DLDO1, DLDO2, CLDO.

It says:

The power supply rails for the AD9106 are AVDD for analog circuits,
CLKVDD/CLDO for clock input receiver and DVDD/DLDO1/DLDO2 for digital I/O and for the on-chip digital data path. AVDD, DVDD, and CLKVDD can range from 1.8 V to 3.3 V nominal. DLD O1, DLDO2 , and CLDO run at 1.8 V. If DVDD = 1.8 V, then DLDO1 and DLDO2 should both be connected to DVDD, with the on - chip LDOs disabled. All three supplies are provided externally in thiscase.
This also applies to CLKVDD and CLDO if CLKVDD = 1.8V.

I don't understand the purpose of all those on chip regulators.

Does it mean that the chip needs 1.8V for circuits associated with CLDO/DLDO1/DLDO2 and they are provided so that you can only use 3.3V supplies (for DVDD and CLKVDD?)

But it says
"Clock Power Supply Output (Internal Regulator in Use), Clock Power Supply Input (Internal Regulator Bypassed)"
It is an output? Why?

What is the purpose of these pins??


I want to use a minimum of external parts to make this chip run. What do I do? Decouple the LDO pins? I just don't understand why they are outputs.