Design feedback on WiFi-controlled phototriac-based mains strobe chaser

[gsuberland]

I'm looking for some feedback on a mains strobe chaser design I made. It uses Vishay VO2223 phototriacs driven from a Microchip MCP23017 IO expander, which itself is driven by a NodeMCU ESP8266 WiFi board. The bulbs I have are Bell 05495 5W LED GU10 (230V), which have since been superseded by the 6W Pro LED Classic series so I got them cheap. I've never used triacs or phototriacs before, so this is a bit of an experiment.

With the PCB design I've tried to ensure maximum isolation between the hot-side and logic-level traces, including drilled channels under the VO2223 parts, but I don't do a lot of mains-level stuff so I'm basically going on common sense and intuition here. This board design is the first revision, and for the next revision I plan to include jumpers for addressing on the MCP23017, and a daisy-chaining connector so that multiple boards can be hooked together and driven from a single NodeMCU board.

Does anyone have any feedback on the design?

(Apologies if the pictures are huge; 4K monitors spoil me for resolution real-estate)

[Twoflower]

Some points I noticed still it's not a complete review:
1. You somehow managed to make the C1 disappear in your layout.
2. Why the additional transistors? The MCP23017 can drive up to 25mA, the LEDs should be driven with 10mA. There's plenty of headroom.
3. You have a fuse for the 230V somewhere? Maybe there's place for it on the PCB
4. Thought about GND flooding?
5. No mounting holes (or just two). You might consider some extra with the long insulation cuts.
6. Not sure how your wiring will look like in the end. With the neutral at a different place than the hot.
7. Rotate the MCP23017 90° clock wise to make the design look a bit cleaner (most top signals go to right).

Are you limited to that form factor? If not: Place the optos in one row and have the terminals alternating hot, neutral. That would allow a cleaner wiring.

[fourtytwo42]

With the PCB design I've tried to ensure maximum isolation between the hot-side and logic-level traces, including drilled channels under the VO2223 parts

Do you mean slots in the pcb ? If so doesn't look like it will hang together as its cut into pieces!
And yes you are correct your schematic is unreadable

[gsuberland]

1. You somehow managed to make the C1 disappear in your layout.

Whoops! You're right.

2. Why the additional transistors? The MCP23017 can drive up to 25mA, the LEDs should be driven with 10mA. There's plenty of headroom.

Good spot. The original design had phototriacs for all pins of the MCP23017T, and it has a maximum current of 125mA, so I used transistors to avoid that limit.

3. You have a fuse for the 230V somewhere? Maybe there's place for it on the PCB

The plug is fused.

4. Thought about GND flooding?

Yup! Will ground flood when the design is completed. This is just the first revision.

5. No mounting holes (or just two). You might consider some extra with the long insulation cuts.

It's a 10x10cm board so it shouldn't be a problem, and I wanted to keep the mains side away from any screws.

6. Not sure how your wiring will look like in the end. With the neutral at a different place than the hot.

It's probably a bit awkward but I'm restricted on size. Thankfully the housings I've got for the GU10 bulbs have really long leads.

7. Rotate the MCP23017 90° clock wise to make the design look a bit cleaner (most top signals go to right).

Good idea. I think I initially had some other components in that area that necessitated me having it rotated like that, but in this design it doesn't make sense. Cheers.

[gsuberland]

Do you mean slots in the pcb ? If so doesn't look like it will hang together as its cut into pieces!

Yes, slots in the PCB. I would've thought that with a 1.6mm PCB it should hold on just fine with the gaps I have there. I suppose I could remove the small horizontal slot near the bottom left VO2223 for structural reasons.

And yes you are correct your schematic is unreadable

Sorry. I can't judge how it should look on inferior resolution screens though. I've attached one where I've zoomed out but it looks tiny on my screen, so no guarantees.

[Twoflower]

1. I really wonder how this missing C1 could happen. 

2. Damn. I missed to check the max total current. But you're still below that.

5. From my point of view that's not the way you should go. The two mounting holes are not sufficient. Especially with the long cuts your PCB that cuts it into bits and pieces you should go at least for four. I would even look if it is possible to have a centre one to stabilize it. Especially with the 22 cables attached to the board. There's a chance that the bending board cause the traces, solder or SMD parts to break.

8. One additional point: What's the designed current? Are the tracks wide enough?

Just another idea: Divide the power part in two boards 5 ports each mounting the second one above the main board.

[gsuberland]

The missing C1 was because I added it after I exported my netlist and forgot to forward-annotate. I'll look into the mounting holes too.

The designed current is very low, even with inrush current. The continuous current is about 25mA per bulb.

I'm limiting myself to the 100x100mm form factor because it has to fit inside a stage light enclosure, but I might do some more measurements and see if I can manage ~120mm so that I can have ten L/N pairs on one side.

[Ian.M]

It violates the clearance requirements of Table 2H of IEC 60950 if the 5V supply or anything connected to it is accessible.  (A slot does *NOT* help clearace.) 
 
It also violates the creepage distance requirements, even if the board and its 5V supply is entirely internal to a grounded case.

There's a handy online calculator for IEC 60950 at http://www.creepage.com/
Use 253V RMS (230V + 10% permitted supply variation) and 358V peak.

As there is a strong possibility of it being used in the same room as a fog machine, IMHO it should be at least pollution degree 3, possibly higher, unless you use a sealed and gasketed case, with only filtered vents.

You've already had the others tell you its a mechanical design disaster.

Rules of thumb:

* Don't route *anything* or put any extra copper under the optos - they are in packages that when used with normal  minimum pad sizes will provide the clearance required, and *may* provide enough creepage distance.

*  Don't make any individual slot longer than 1/5 of the board dimension in that direction or for multiple slots, a total of more than 1/2 the dimension along the same line.

* Provide mounting holes at all corners or other mechanical support (e.g. PCB guides along sides) and near any screw terminal blocks. All live area mounting holes and support locations must have appropriate creepage and clearance if you are using metallic fasteners or mountings.

[gsuberland]

Thanks for the reply Ian. Interesting info there. I guess the parallel traces near the top could be considered too close, although I had considered the use of fog and do plan to apply a conformal coating which should reduce the minimum required distance (I have DRC set to limit minimum trace distance to 1mm) and should protect the board against any pollutants.

I have to admit that I'm not used to designing this kind of equipment, so the design rules on this are a bit new to me - I didn't actually know there was a standard for it. Just as a refresher, am I right in thinking that creepage is the distance between conductors along the insulating surface, rather than through an insulating material? Do you have specific examples of where creepage and clearance are violated on this design so that I can keep them in mind?

I think I'm going to redo the PCB using the advice from this thread and try to keep the trace distances much further apart, with a 120mm board so that I can have L/N pairs rather than completely split rails. On that front, are the slots actually a good idea from an electrical safety perspective, ignoring the mechanical problems in this specific design, or should I just rely upon the resistance of FR4? Would it also be prudent to consider increased PCB thickness over the standard 1.6mm?

[Twoflower]

Probably you can use two edges for the high voltage (e.g. lower and right). Placing the optos as close as possible to the connectors. That would keep the HV area in that area. And squeezing everything in the LV area a bit and removing the transistors you might be able to stay easily at 100mm x 100mm. Maybe you can even fit the GPIO extender beneath the NodeMCU. But I don't think that is required if you clean up the board.

Just make sure the ESP antennae is pointing to a edge. For a design with the ESP210 I placed a no copper area beneath the antennae. And why do you use that huge and expensive board anyway if you don't use the additional pins? If you have the space, you can probably add the possibility to switch to the cheap versions by placing an alternatively mounted header for the small ESP boards.

[Ian.M]

Clearance is distance as the crow flies - i.e. a straight line through air.  It can go round corners if there is a solid insulating barrier of adequate breakdown voltage in the way, but is always the shortest possible path, including through a tiny crack between two insulators only mechanically fastened together. Its the distance an open air arc has to jump for it to fail.

Creepage is the distance measured along an insulating surface and, together with the insulating material and its surface condition and treatment, determines its resistance to failure by conductive tracking.   

Clearance distance is the dominant one - if its no good, creepage distance is irrelevant.

Your design violates clearance (and creepage) at all the optos between pin 8 and the  Line track under them.  There's a dammed good reason why their package omits pin 7!  It also fails between their output tracks, which may have up to 253V RMS between them with one channel on and an adjacent channel off.   For that region, according to www.creepage.com, and assuming pollution degree 2 you should be maintaining 1.5mm min. clearance and 4.1mm creepage for functional insulation between tracks/pads on the same side of the board.   You'll get a bit more creepage rating from your confomal coating, but unless you are set up to test the board surfaces for contamination and surface resistance before coating, then perform a 100% UV inspection of the coating for defects in critical areas, don't count on the extra the coating gives you.

It also probably fails clearance between that Line track and the copper linking pins 1, 3 & 4 on the LV side of the optos.  You need 4.0mm clearance (Reinforced insulation) if any  metal part on the LV side can be touched or if there's external LV cabling.   It fails creepage at the isthmus between the slots between the third and fourth optos down. You need 5.1mm.

N.B. the optos aren't rated for pollution degree 3 or higher - you are going to need that sealed case with cable glands and a filtered vent if there's any chance of it being used anywhere near a fog or smoke machine.

Other design fails are the lack of any provision for snubbers or gate pulldowns to redce false triggering if it proves problematic in service.  That sort of thing needs to make it into the prototype and any beta test run even if its DNPed then  once you have enough boards out in the wild, *IF* you've never needed it *AND* you need to do a board shrink, you can delete the extra footprints on the next respin.

FR4 has adequate insulation breakdown voltage for a Line track on one side crossing a Neutral on the other to be no particular problem unless the board is compromised by excess heat or mechanical stress.   I wouldn't trust Line/Neutral on one side over a LV circuit on the other.  A thicker PCB will be stronger, but electrically its not essential.

Minimise your slot lengths -  there's no point in any of them extending more than is required to maintain >7mm creepage as that's all the opto bodies give you.  Maintaining mechanical strength is essential, and if the board cracks at or near the end of the slots, the cracks can trap contamination and encourage tracking over or through the FR4, or a power track can crack, arc and char the board till it fails..

[gsuberland]

Amazing feedback and info, thanks. Really useful. Particularly a good point on the removed pin on the VO2223; I used an 8-pin DIP footprint because I was lazy and never considered the clearance problems, but it's clear now that I can't be so blazé. Also I hadn't realised that individual components have pollution degree ratings, so I'll keep that in mind for future component choices!

I'm going to do a full board redesign based on all of this info and should hopefully end up with a much safer and more sensible design.

W.R.T. to sealing the optos against pollution, would it be sufficient to apply a conformal coating and then pot them all in epoxy resin, assuming I use a nonporous electronics-safe product? Once the boards are tested I have no interest in component-level repair if an opto fails; these boards are only being used by me so it's not like I have to worry about one dying "in the field". I plan to stick the whole board in an IP65-rated box inside the outer case, although I hadn't thought about rubber grommets or sealants.

One thing I didn't quite understand was the point about the missing pulldowns. Did you mean that NMC_D1 and NMC_D2 are missing pulldowns?

I understand your point about snubbers (although I've never used them), but if I were to redesign the circuit to remove all of the transistors as per Twoflower's suggestion and just do direct drive from U1, should I place an RC snubber between each GP pin on U1 and ground alongside 10k pulldowns, or just omit snubbers in this case since the transistors are no longer present?

Again, thanks for all the help so far on this.

[Ian.M]

No, a gate pulldown for the opto-Triac would go between pins 5 and 6 - its probably not needed but if you don't have the pads, you cant fit one later.   Somewhere around 1K would *probably* be appropriate - only fit if if you are getting false triggering and a snubber didn't help.   

The snubber is a series connected R-C network between pins 6 and 8.  Together with the load inductance the capacitance limits dV/dt across the TRIAC in off state, and controls dI/dt and dV/dt at turnoff to prevent re-triggering.  The snubber resistor must also limit the current from the snubber capacitor at triggering to prevent the TRIACs maximum current being exceeded.  The calculations for a snubber are quite complex - most TRIAC manufacturers have application notes with the design equations.  The resistor only transiently has a high voltage across it so can usually be physically small (subject to availability of an appropriate voltage rating n that form factor, but the capacitor must block the full line voltage when the TRIAC is off so must be rated appropriately.   Unfortunately you need to do the math to get an idea of the likely snubber components before you can add unpopulated footprints to allow them to be retrofitted.   Additionally, when switching a capacitive load, a small series inductance may be needed in the load circuit to limit dI/dT immediately after triggering.

[gsuberland]

Makes sense. I had considered transients from the load but assumed (perhaps incorrectly) that the TRIACs would handle it without problems.

The calculations, if I read them correctly, want to know what the parasitic capacitance of the TRIAC is, but the VO2223 doesn't list one. I read that I can estimate it as anywhere between 100pF and 1nF, does this seem sensible? They also want the load inductance, which is an unknown for me, and the bulb manufacturer certainly doesn't list it. So I'm kinda guessing here.

I would imagine that I'll want a 10nF cap rated in excess of 520V (358V peak, +20% for cap tolerances, +20% for safety margin). Based on that, a 1kV X7R ceramic should be more than sufficient, and I can pick those up fairly cheaply in 1210 and 1812 packages. Should I consider creepage distance when selecting the capacitor package, and try to keep the inter-pad distances above 2.5mm, i.e. preferring the 1812 over the 1210?

For the resistor I'm less certain on value due to my lack of data. 120 ohms seems to be the common value.

What are your thoughts on manual part selection of parts vs. a single snubber unit? e.g. http://uk.farnell.com/roxburgh/re1201/rc-network-250v-0-1uf-120r-pcb/dp/2336109

Apologies if I'm going off on the wrong track here. Without solid data on the load inductance and parasitic capacitance of the TRAIC, I feel like it's a bit of a crapshoot to try to run through the calculations. GIGO and all that.

[Ian.M]

Consider when the TRIAC triggers - the snubber R suddenly has the whole snubber C Voltage across it, which could be worst case nearly 360V if it fires at the peak of a 10% above nominal mains waveform.    That certainly favours larger package SMD parts, although if you think you aren't going to need them, through hole pads near pins 6 and 8 would take less board aria - if you have to populate, use an axial cap and a resistor mounted vertically and join them in mid-air!

I'm afraid there is no substitute for doing the math.  I expect that 120R common snubber R value would be for a much higher TRIAC current rating, and probably needs scaling to keep the peak current low enough for a 0.9A rated TRIAC 

For the LED bulbs, they probably look rather capacitive.   Inductance is going to be dominated by the wiring unless you add chokes to control EMI and dI/dt.

[gsuberland]

TH probably makes more sense for that case now you mention it. I'll do the circuit and board redesign and come back once I've got that down. I can worry about RC snubber part selection later if it becomes a problem, but I'll keep ~1200R and 10nF in my head as a rough starting point, since you're right that 120R is a bit low (I found it as an example value for a 10A rated TRIAC).