My system has a 9V battery as the main power supply. There is a 4-position switch as well; in the system off state, position 0, the switch poles are open. Positions 1, 2, and 3 short the switch's poles to ground individually. This allows me to interface the switch with GPIOs on my uC for function selection, by virtue of external pull-up resistors on the uC GPIO pins.
The LDO has an enable pin which must be driven logic high.
I want this enable pin driven high when the switch pulls any of the GPIO lines to ground. The problem is, I cannot think of a circuit which will allow me to use the 9V (always-on) supply and interface with the 3.3V side of the uC without drawing current into the uC while in shutdown.
Here's an illustration. Only a single switch pole is shown, but the idea is the same between all the GPIO lines. I've modeled the 3 GPIOs as typical ESD rail to rail diodes & 50p / 1meg input impedance:
What circuitry can I use to achieve this function? In the off state, the VDD supply is sitting at 0V, so I cannot rely on VDD to power any logic gates. I could power logic gates from the 9V supply, but then I have 2 problems: a level mismatch between the GPIO expectation of 3.3V nominal logic levels, and the 3.3V and 9V supplies fighting for dominance. There must be a way to bridge the 9V supply leg with the GPIO lines, perhaps by sensing current from the 9V rail to ground, but I cannot come up with a circuit to do this safely for the GPIO lines.