Design advice: Clock/pulse generator output circuit

[fourfathom]

I'm not a fan of this method because I don't find it really proper. Output impedance and slew rates tend to vary quite drastically when changing the supply voltage of these chips as you said.

Slew rates, maybe. Output impedance... I wouldn't be so sure before testing it in actual hardware.

Could be, on the output impedance.  The specs show VoH and VoL vs load current, which I am using as an indicator of output impedance (and it matches up reasonably well with my measurements), and this does vary with supply voltage.  I've only used this method with a fixed 3.3V supply so I've never checked it with varying voltages.  One thing I did was to drive multiple buffers in parallel (each with their own output series resistor).  This reduced the effect of variable buffer output impedance, as the fixed resistors dominated.

[PCB.Wiz]

Yes, buffers and parallel buffers will work ok for 3v3 and 5V, but the OP wanted to reduce power supply over a wider range.

Down at 1V ballparks a simple buffer will run out of gate drive, but a SPDT Analog Switch, which uses the full logic supply for the mosfet transmission gates, will be fine down to 0V.
 

[fourfathom]

Yes, buffers and parallel buffers will work ok for 3v3 and 5V, but the OP wanted to reduce power supply over a wider range.

Down at 1V ballparks a simple buffer will run out of gate drive, but a SPDT Analog Switch, which uses the full logic supply for the mosfet transmission gates, will be fine down to 0V.

Agreed!  In my defense, the original requirements were a bit flexible.

[shapirus]

Could be, on the output impedance.  The specs show VoH and VoL vs load current, which I am using as an indicator of output impedance (and it matches up reasonably well with my measurements), and this does vary with supply voltage.  I've only used this method with a fixed 3.3V supply so I've never checked it with varying voltages.

And I actually measured it, but at a fixed 5V: for a few SN74LVC1G04 in SOT-23-5 it was ~12-12.5 Ohm, which turned out to be ~30% higher than the value which could be derived from the datasheet IIRC.

That's actually interesting, I think I have some soldered to a breakout adapter board, maybe will test again with a varying voltage when I have time.

[ProtonFox]

I see there is a little debate regarding the output impedance. Never measured it IRL in fact, that's what I saw in the datasheets. I'd be interested as well to see the actual measurements, if someone does this. I'm away from my lab for a few months (hence my extra time for simulations) and apart from generic, slower and older CMOS/TTL inverters I don't have comparable parts yet.

Going back to my main subject, I'd like to have your opinion on my simulation model.

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I redrew the concept of my behavioral model of the switch on KiCad so it looks less messy. I took the NX3DV221 switch as a reference, which claims to have a maximum 6  ON resistance and a parasitic capacitance of around 5-6 pF parasitic capacitance which actually varies between the state. It is not as accurate as an actual model, but it can allow me to have a rough idea of the part's flaws. Is this circuit not too far from the reality ? I used this Analog Device's application note: https://www.analog.com/media/en/training-seminars/tutorials/MT-088.pdf to be sure about the parasitic elements but it's only about SPST switches.

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This is a simplified schematic of how I wired the switch, where it should switch between the adjustable voltage and 0V. The actual simulation schematic is attached for information. The 2 ports subcircuit is the transistor voltage regulator circuit I borrowed from PCB.Wiz. Don't pay too much attention to the filtering cap; I just slapped it without calculation, but I know a combination of capacitors will be needed so the ripple is kept low enough on both high and low frequencies. It gave somewhat acceptable results on the simulation anyway.

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And finally, here are the simulation results. It looks decent but has some little quirks. As you can see the risetime is pretty fast so it seems to perform well, but the falltime is longer, just as if parasitic capacitance take longer time to discharge. It's still within my specifications (~ 2 ns) but I wonder if something's wrong with my model.


Edit: damnit, how do you add pictures?

[ProtonFox]

Pictures attached, as my previous post didn't turned out how I expected.

[ProtonFox]

I continued to work and experiment with this simulation.

I added some slight parasitic elements to the switch's model : bonding wires inductance and leakage currents. Did not change anything apart from slight overshoots/ringing, but I may have overistimated these parasitic elements so I'd take them with a grain of salt.

I checked the current waveform at SUB2's output (the voltage regulator), I get ~60 mA spikes when the load is matched and output at max level.

I'm now working at making a proper filter between the voltage regulator and the switch, and taking passive component's flaws at high frequencies, capacitors Q factors and such. It's a bit of work, I fell into the rabbit hole of capacitors dielectrics, and came to the conclusion I needed C0G / NP0 capacitors. Afterwards, I had enough information to model a somewhat realistic capacitor.

When playing around with this filter, I tried to add some kind of RF choke (a somewhat high value inductor) between the voltage regulator output and the filtering capacitor. The results were almost identical, so no problem. Maybe using a programmable LDO to perform this function is not that bad, after all. They would at a first glance fit well this purpose.