1. Doesn't matter, electrical length is far shorter than the signals care about (that's going to be at most, what, 50MHz Q/SPI, with few-ns edges?).
You also have enough width/space to get traces between SOIC pads.
BTW, keep enough clearance between vias and pads, so they don't suck up solder. Alternately, fully tent them (top and bottom).
- Also note, anywhere you have vias, you have negative space (clearance) in the opposite plane(s). A close row of vias can break quite a slot in the plane(s). Around the MCU? it doesn't look dense enough to be a problem so that's good, but there is the column of vias on the LCD? connector that might be tight enough to do this. These could alternate sides to double the spacing in each column.
Generally speaking, I don't like more than three or four vias in a tight group; if working with higher speed / low noise signals, try for fewer around the respective traces. Further: where e.g. a high speed signal or diff pair crosses layers, a bypass cap or two can be added adjacent to the via(s), so that the image currents can transfer from top to bottom, through the cap and plane impedances together.
- Speaking of caps: anywhere you have bypass caps, you can basically double their effect by flanking both sides with vias. The via and trace inductance act in parallel this way. Whereas the lengthwise arrangement has maximum component body, trace and via inductances. The trace can also be wider, or obviously shorter, up to whatever limit the via (tented/not) dictates.
2. If I should assume this is USB Full Speed, it's just another CMOS logic signal. Differential routing doesn't matter, length matching doesn't matter, trace impedance hardly matters. Not at least to any kind of scale that would matter on-board. If it's High Speed, these lengths are still within tolerance (check the spec, it's free
), and indeed you can still do...
- ...Why not route USB through the other pair of ESD diodes? Can bulge out around the power pins, so the connector-facing pair picks up the inside corners (diagonal connect) of pins e.g. 1 and 6, traces loop around 1-3 and 6-4, and diagonal connects to 3 and 4.
Probably not even a big improvement, as clamping performance is limited by power pin inductance (again, can use wider traces/vias -- treat these pads as if a bypass cap), but it'll still account for the ESL of the clamp pins themselves, and internal resistance, acting in parallel so dropping the peak clamp voltage.
And I'm guessing it's a one of those diode-clamp-into-TVS types, so you're not at risk of blowing out line capacitance limits in this way.
In any case, get rid of that extra trombone length under the connector, that's not doing anything for 'ya. Also regarding the alt: avoid acute angles, mainly just 'cuz they look bad. The tee joint can be a tee, angling it towards the connector pad doesn't do anything.
Also the, what's the short other connector, oh maybe it's a really stubby uSD slot? ESD diodes might be desirable there, though if it is indeed SD, yeah doesn't really matter.
Or the big pins on the right edge, no idea if those see any kind of current, or what the series chip components are (current limiting? filtering?), but the size of the connector suggests some amperes of capacity so the traces look rather thin in comparison. Also if those are resistors, wider traces can be used to improve heat dissipation from them. And the transistors? driving them, either should be digital/prebiased BJTs (if low current outputs), or should have series resistors at the MCU, whether for [bare] BJT (current limiting is mandatory!) or MOSFET (series gate impedance reduces EMI and risk of oscillation).
3. V is better. The difference in stub length is only a few nH, but strictly speaking, that's a few nH saved.
4. Doesn't matter, it's just a dumb connector. Like you say, signals are on Top / ref GND so this layer is irrelevant. You might still route it on Mid2 or Bottom for convenience (also, is there a keepout area under the connector body?).
- Also note that the big slot in the middle (LCD cable passthru?) won't have square corners. If you need square corners, relieve them with an extra cutout with a specified radius. Or specify what radius you actually need. Typically board rout is done with 1mm, and finer will cost extra for tool change/wear. It looks more than wide enough so that a little rounding won't matter here, but FYI -- avoid ambiguity, and extra-tight corners, when it does matter.
Y'know, this is pretty low density overall anyway, it could be just two layers. The planes aren't doing anything that a well-stitched top/bottom pour can't do, and with direct routes for most signals, there aren't even a lot of crossings. (Crossings are critical in 2-layer builds: you always want a trace over an opposite pour, so crossing traces create a negative space on both layers. Keep these areas small -- bunching traces into buses say -- and stitch around the crossing with 3+ vias to minimize the loop area for currents flowing around the edge of that negative space.)
And, that's about everything I see. Maybe you'd like a TVS on VBUS, looks like it's supplied from/to several connectors? Can mitigate problems with hot-plugging. Likewise some supply impedance to the uSD can avoid brown-out on hot-plugging (cards are allowed up to like 8.2uF onboard, compare that to your board's total 3V3 capacitance! -- and likewise, they're allowed onboard bypass, don't worry about trying to bypass the pins at the connector, some impedance here is fine, say a couple ohms as current limiting). Don't know what your regulator is like, if it needs ESR or other compensation. Do see a lack of thermal vias on it, but maybe the load and drop are small enough not to matter. RS-485?, maybe some ferrite beads or additional filtering, but it's somewhat uncommon for it to be an EMI problem, it's a well behaved standard.
Tim
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