ADC with built-in fixed LPF, available in 3 speeds?

[fcb]

Looking at ADCs. Found these three TI converters:

ADS8681 (1000 ksps)
ADS8685 (500 ksps)
ADS8689 (100 ksps)

All appear on the same datasheet and appear to have the same fixed 2nd order LPF (-3dB @ 15KHz).  Small deviations between versions regarding SFDR, THD, SINAD, but apart from that seem identical.

Any thoughts on why the 500 and 1000ksps versions exist as there is essentially no apparent benefit in sampling quicker??

[Kleinstein]

The filter attenuation at 50 kHz is not yet very good. So one may really want more then 100 kSPS if the signal source does not have it'S own BW limiting / filtering.
So the 500 kSPS makes sense, likely to be used with some digital low pass filtering an decimation added to the digital side. Oversampling can improve the SNR a little.
The 1000 kSPS speed may not be such a big thing, possibly the same design, just selected ones.

[radiolistener]

Any thoughts on why the 500 and 1000ksps versions exist as there is essentially no apparent benefit in sampling quicker??

If your project needs to avoid aliasing noise and images, it needs very wide gap between antialiasing LPF cut-off and Nyquist border (Fs/2). This gap allows to place LPF slope where rejection is not good.

This is why recommended sample rate is 10-20x times higher than AA LPF cut-off.
So, if your LPF cut-off is 15 kHz, then recommended ADC sample rate is 150-300 kHz.

But there is also another issue, since analog LPF has bad flatness near cut-off, it's better to use LPF with 2-3 times higher cut-off to get good flatness and then apply LPF in digital domain to get almost ideal flatness. In your case it means that for 15 kHz working bandwidth you're needs to use analog LPF with 30-50 kHz cut-off and about 600-1000 kHz sample rate. In that way you can get high out of band noise/image rejection, the best flatness and linear phase within required 15 kHz bandwidth with using high order FIR LPF which has almost ideal flatness, very sharp cut-off slope and high 100-150 dB rejection in bandstop region.

But it depends on your needs, do you really needs very good filtering and ideal flatness?
If so, then these expensive solutions are worth the effort.

Good quality high dynamic range signal requires expensive components and large computation resources which is also expensive. So, the quality needs to pay more money.

[MasterT]

Analog Device has similar division like ad7988-x, where X  indicates 100 or 500 ksps. Since adc is running at unknown internal clock, and has very unprecise  conversion timing, I suspect this internal clock been adjusted at the last production phase. Same way as OP amp "graded" depends on offset or whatever parameters needs better specification.

[fcb]

Any thoughts on why the 500 and 1000ksps versions exist as there is essentially no apparent benefit in sampling quicker??

If your project needs to avoid aliasing noise and images, it needs very wide gap between antialiasing LPF cut-off and Nyquist border (Fs/2). This gap allows to place LPF slope where rejection is not good.

This is why recommended sample rate is 10-20x times higher than AA LPF cut-off.
So, if your LPF cut-off is 15 kHz, then recommended ADC sample rate is 150-300 kHz.

But there is also another issue, since analog LPF has bad flatness near cut-off, it's better to use LPF with 2-3 times higher cut-off to get good flatness and then apply LPF in digital domain to get almost ideal flatness. In your case it means that for 15 kHz working bandwidth you're needs to use analog LPF with 30-50 kHz cut-off and about 600-1000 kHz sample rate. In that way you can get high out of band noise/image rejection, the best flatness and linear phase within required 15 kHz bandwidth with using high order FIR LPF which has almost ideal flatness, very sharp cut-off slope and high 100-150 dB rejection in bandstop region.

But it depends on your needs, do you really needs very good filtering and ideal flatness?
If so, then these expensive solutions are worth the effort.

Good quality high dynamic range signal requires expensive components and large computation resources which is also expensive. So, the quality needs to pay more money.

It seems flawed that if you want a say 12KHz BW then you would choose to sample at perhaps 50x, even if you are using an FIR.

Our application is somewhat akin to a 'scope and measuring at ~100KHz. With the particular waveform I actually care about settling time for the front end - I excluded the AD8689 family in the end.

[radiolistener]

It seems flawed that if you want a say 12KHz BW then you would choose to sample at perhaps 50x, even if you are using an FIR.

No, that is pretty good way if you want to achieve the best dynamic range with low non-linear distortions. Because when you sample signal at 50x higher sample rate you can get additional SNR gain due to FIR LPF processing gain. This is very expensive solution and may require high power consumption, but it allows to get the best results for signal quality which is impossible with other solutions.

For example with 50x higher sample rate you can get 17 dB processing gain which equals to adding 3 bits to your ADC resolution


Another example is oscilloscope which needs to avoid incorrect waveform distortions on the display due to high frequency images and aliasing. This is why oscilloscope also uses pretty large gap between RF frontend LPF cut-off and Nyquist border (sample rate/2). This is why 100 MHz oscilloscope requires min 1-2 GHz sample rate to show proper signal waveform.

[Kleinstein]

Doing oversampling and than digital filtering and decimation back to the final data rate is a pretty common technique. Ideally one would have the upper BW limit set by the predictable digital filter and not by the analog AA fitler. So one would ideally use the ADC not all the way to 12 or 15 kHz, but more 5 kHz. For the other direction (DACs) oversampling is pretty standard with CD players.

With the modern capacitive ADCs there is relatively littler extra costs and power penelty to get the 500 kSPS or 1 MSPS speed. The processing power for the filter part is also not that bad - the fast SPI interface is a bit inconvenient. So it might be nice to have the digital fitlering already in the ADC chip side to reduce the data rate.

The slightly odd thing is why they don't higher a higher analog fitler BW, like some 30 or 60 kHz for the 1 MSPS version.

[radiolistener]

So it might be nice to have the digital fitlering already in the ADC chip side to reduce the data rate.

such solutions use pretty bad filters performance (due to power and cost economy) so it usually worse than you can get with custom filters stack implemented on FPGA