MCP3564 (ADC 24bit 156ksps) Only reading zero [solved, dirty trap]

[Berni]

I have been struggling with getting a MCP3564R ADC chip for multiple days.

SPI communication works fine. The chip takes in register writes and can read them out nicely. However the ADC result register is always 0x000000. The Data Ready flag toggles up every so often just like it should, but still all zeroes

Later on i found a bit of a minefield of reserved registers that must be set to 1 in order for the chip to work, did forget to set one of those to 1 indeed. Still didn't work.

Then went down a laundry list of things to check:
- Changed the sample rate and observed the 0x00000 results coming out faster or slower
- Tried combinations of external or internal voltage references
- Enabled the internal clock output pin and seen it producing a nice stable square wave
- Checked the soldering multiple times. Including poking pins with tweezers
- Checked all the supply voltages multiple times.
- Swapping to a brand new chip
- Checked SPI signal integrity, looked clean
- Slowed down SPI a lot
etc...

Yet still getting all 0s as the result. 

Getting desperate i decide to check the IRQ pin that i am not using (since i plan on polling it at a low speed). So since i don't need it i just leave it floating. But hey lets scope it out in case it sheds some light on it, i am running out things to even try. Next idea was to order a evaluation board for that chip. Then i read up how the IRQ pin works and find this....


Wait what...
 

Why the hell would you do that?! Screw you Microchip!

Well looks like the edges on IRQ pins are used to help synchronize together multiple chips when being used in the raw MDAT mode where it barfs out the raw 4bit sigma delta modulator values. But even if you don't use that mode the IRQ pin maintains this functionality. So the chip will be running fine yet the modulator would be sitting still and doing nothing because it is permanently waiting to be synchronized with 'other chips'.

So i just reconfigured the IRQ pin to be a push pull instead of open collector and it WORKS!

I am leaving this as a thread here in case someone else runs into the same dumb nonsense problem.

[MasterT]

Be advised, that adc is suceptable to switching noise getting back from this pin. I was able to detect noise level difference when 10 k or 100 k resistor was installed as pull up.

[Berni]

Ah thanks for the tip

My use case for the ADC is just fairly slow measuring of voltages and currents around a test system. So noise is not as critical.

[Siwastaja]

What utter bullshit from Microchip. That note should be in big red font and IN TOTALLY DIFFERENT SECTION, like basic functional description plus pin listing. Because it has absolutely nothing to do with interrupts. It is obvious that if you are not using a feature, you would be skipping the section discussing it.

[Berni]

Yeah i would have expected a big warning "DO NOT FLOAT" next to the pin description for the IRQ pin or something. Not buried in the middle of a big wall of text for a optional feature i don't even want to use.


Well since this is  apparently a weird chip i looked trough the datasheet to make sure i am doing other stuff correct. Along the way double checked i have my SPI settings in order, so i looked at the SPI timing diagram in the datasheet:



Alright, So we can do SPI mode 0 or 3 very good.
Wait..
The SDI appears to be changing on a falling edge, but then the SDO appears to be changing on a rising edge.
Doesn't SPI change both data directions on the same edge? *checks wikipedia* Yep it should... Oh crap is this a non standard SPI?!?! How am i going to convince my STM32 to do that. 



Off to the logic analyzer and... nope this is just normal SPI mode 0. So the datasheet diagram is actually wrong. The SDO pin does indeed change state on a falling edge as one would expect.
Crisis averted.



Reading the description instead gives you the correct idea too. So just the diagram was drawn wrong.

Microchip what were your engineers smoking when making this damn chip?!

[hli]

The diagram says 'the devices latches SDO on the falling edge', which would be correct SPI. Yes, the diagram looks off.

[DJKick]

On the IRQ issue, there is a feedback from the pin back to the chip so that the latching of the new data cannot come before the IRQ feedback is recognized. This avoids cases where data is updated before IRQ is recognized by the MCU on the board.
About the interface timing diagram, the bar that defines tDO is starting on the falling edge of SCK. The graph may look like it is aligned on rising edge but it is not the case, the tDO vertical bars are explicit.

[stowwest]

On the IRQ issue, there is a feedback from the pin back to the chip so that the latching of the new data cannot come before the IRQ feedback is recognized. This avoids cases where data is updated before IRQ is recognized by the MCU on the board.

geometry dash world

About the interface timing diagram, the bar that defines tDO is starting on the falling edge of SCK. The graph may look like it is aligned on rising edge but it is not the case, the tDO vertical bars are explicit.

Great, my issue has been resolved by completing the interface timing diagram.