Current source feedback capacitor

[OM222O]

I tried it and even without R8 and C1 it never passes -180 degrees which I assume is the point at which the op amp starts to oscillate?
worst case was about -165 degrees at about 13MHz


but with the suggested values of 10k and 100nF it seems to never go below 80 degrees:


My intention is to also eliminate the op amp characteristics should not show up but I'm not sure if there is a way around the phase margin of the amp?
I'm not sure how to interpret the graphs but I assume if at any point the phase is lower than phase margin of the op amp I will have oscillations and the components add a pole to gain back some phase?

[D Straney]

Good loop analysis going on here.

The ADC inputs are all protected via 1k resistors (RN1 & RN2), then they have a 1nF X2Y (feed through) capacitor which suppresses noise to ground and a 100nF capacitor which suppresses differential noise (both are C0G caps and the X2Y is capacitance matched) although I screwed up the resistor network purchase and there is no matching (they are 1% tolerance) but I didn't have issues with differential noise in the few prototypes I have made and I really don't want to re order 250 resistors if they're not causing issues 

Oops yeah my mistake, I completely missed that resistor network somehow.  Wouldn't worry about matching, even if one is +1% with +5 nA and the other is -1% with -5 nA, the error is still only 0.1 uV.

For the reverse polarity I actually plan on using a P-Channel fet (DMP3099L-7 ) since I also have a bunch of them ordered from V2 (it was used as soft power but the new LDO already has that option) which means I can re-use the same parts and it also adds battery life since there isn't a 0.7V diode drop. win-win if you ask me   

Great, even better!

for the resistors I honestly couldn't get anything better unless approaching insane territory (>1$ per resistor) which would obviously blow the budget so I'm happy with these. I would have liked a better 1ohm resistor however they only come in massive packages since I chose a high power rating, >2W to be exact to give some margin, I don't like to run a 1W resistor at 1W, even if it's a pulsed load) and they are less optimized for tempco / absolute tolerance. I can calibrate out the constant errors using a milliohm meter (funny how it's always so much easier if you had one of the things you were making, to help you with making it   ) which I don't have. maybe someone can calibrate one unit for me and I'll be able to use that for the rest, but that will have to wait for later.

Yeah I'd agree on all of that: the parts you have seem like the right choice for what you're doing - going an order of magnitude better in accuracy would need a whole next level of complexity and cost in parts (plus calibration!).

I really appreciate the time you put into these posts and it feels nice to have confirmation that I'm not doing things totally wrong from an experienced engineer. Best of luck with the tests and I hope you have more of them  that way I will be able to get more valuable information 

Ha, glad to hear it.  No more long tests for the moment, unluckily / luckily, but sounds like it's all going well and the design's solid!  Just one last note, on the stability: what you're trying to avoid is not the phase dropping below the phase margin of the op-amp (that's more of a "derived" parameter, when using the op-amp closed-loop with a gain of +1 I think), but instead you're trying to keep the loop's phase from getting too close to 0 degrees (around the whole loop) or 180 degrees (ignoring the negative feedback).  This article probably explains better, although you can ignore the "Limitations" section for the first pass: https://en.wikipedia.org/wiki/Barkhausen_stability_criterion

[Jay_Diddy_B]

Hi,

I have modified the model a little so that it will step through the four current ranges and produce a Bode plot for each range.





I have attached the LTspice model.

For this opamp these values of C1 and R8 are pretty good.

Regards,
Jay_Diddy_B

[OM222O]

I tried running the simulation with all 6 ranges and the spice model of max4238 which I got from maxim website. with a capacitor value of 1nF the test would not get past run 1 and would be stuck on run 2!

I increased the capacitor to 100nF and it finished very quickly. I'm not sure what that means.does taking way too long to finish a run mean an error in the circuit?
I also tried increasing the points per decade to 1000 and the frequency range to 100Meg and the test again got stuck for a long time and I canceled it. I'm not sure if I'm doing something wrong
anyways, here is the result I received:


I'm still not sure what should I look for on this graph? in the AC analysis what is the indication of oscillations? a phase of 180 degrees? what is the frequency range that I have to simulate over?

The schematic and maxim file is attached.

[Jay_Diddy_B]

Hi OM2220 and the group,

First the V4, injection source should be moved to the output of the opamp:



The requirement for a low impedance on one side and a high impedance on the other side was not met when the value of the current sense resistor is high.

If I do this:



I have replaced the opamp with an ideal opamp, gain 120dB, infinite GBW.

I get these results:




If I take the idealization further and replace all the parts with idealized models I have:




The results I get are:



This can be useful to see how the real components impact the loop response.

I have attached the LTspice models.

Regards,
Jay_Diddy_B

[OM222O]

That fixed the simulation problems but the main point still remains:

I have no idea what these numbers mean, which defeats the purpose of the simulation 
What are we looking for here? what is the frequency range to simulate over (i.e: why only 10Hz to 1Meg, not 1GHz for example?)
What does V(b)/V(a) show? aren't we just adding an AC source to the output of the op amp?
a small explanation as to what this all means would be very very helpful since regardless of how much I searched, this makes little sense to me. thanks!

[Jay_Diddy_B]

That fixed the simulation problems but the main point still remains:

I have no idea what these numbers mean, which defeats the purpose of the simulation 
What are we looking for here? what is the frequency range to simulate over (i.e: why only 10Hz to 1Meg, not 1GHz for example?)
What does V(b)/V(a) show? aren't we just adding an AC source to the output of the op amp?
a small explanation as to what this all means would be very very helpful since regardless of how much I searched, this makes little sense to me. thanks!

Let me take a much simpler circuit:


This is an non-inverting amplifier with a gain of 2.

I have added a disturbance source V3. The op-amp will try an maintain the output at 2V, 2x the voltage on the +ve input.

If I look at the signals V(a) and V(b) with respect to ground I see:


That most of the disturbance signal appears on V(b), it is trying to reject the disturbance.

There is a very small amount of the disturbance on V(a).

If the opamp had unity gain, equal amounts of the disturbance will appear on V(a) and v(b).

Note that the phase shift between v(a) and v(b) is 90 degrees.

The gain is the amplitude of the at v(b) divided by the amplitude of the signal at v(a). Hence the expression:

Gain = v(b)/v(a)

This is a single frequency measurement take in the time domain.


If I move to the frequency domain, I make this measurement at many frequencies:







This is loop gain.

Since it is the 'loop' gain it can be measured at several place in the loop.

Regards,

Jay_Diddy_B

[OM222O]

This makes a lot more sense now! so if I plot and for each range I look at the point where the gain is 0db (i.e gain = 1) and the phase margin is not near -180 degrees, then my circuit is fine, but if it is near or below -180 degrees at that point, then the circuit oscillates. correct?

[Jay_Diddy_B]

This makes a lot more sense now! so if I plot and for each range I look at the point where the gain is 0db (i.e gain = 1) and the phase margin is not near -180 degrees, then my circuit is fine, but if it is near or below -180 degrees at that point, then the circuit oscillates. correct?

Yes.

As shown in the examples above the phase axis is phase margin. You should have a phase margin greater than 45 degrees when the gain is 0dB.

Gain margin is the negative gain (attenuation) when the phase margin is 0 degrees. It should be -6db or more attenuation.

If you have a single dominant pole both of these conditions are met.

In the example I gave the dominant pole comes from the opamp.

The opamp gain phase response is given in the datasheet:



The gain is -4dB at 1MHz.

The simple circuit, in my previous message, measures -9dB at 1 MHz. The divider, R1 and R2 provides -6dB of loop gain.



There is a 1dB difference between the model and the datasheet.

If I introduce capacitor C1:



There is now a pole at the frequency

F = 1/(2 x pi x (R1 in parallel R2) x C1)

= 31.8 kHz

If I measure the response:



I get -6dB at 31.8kHz, 0db because the RC filter is at 31.8kHz and -6dB from the divider for a total of -6dB.

In this case the circuit behavior is determined by the passive parts, not the opamp.

Regards,

Jay_Diddy_B

[OM222O]

I ran the analysis with the final values of the components and I'm pretty happy with the results (phase is about 94 degrees on most ranges and about 80 degrees on the 10uA / 6th range)

also attenuation is better than -46db when the phase is at 0 degrees (I was not aware of the -6db rule / gain margin before). Again the schematic and the maxim part are attached. can you double check the results so I can be sure I haven't made a bone head mistake somewhere?
Thank you!

[Jay_Diddy_B]

Hi OM2220 and the group,

I have been thinking about the differences between the idealized model and the full model. I have arrived at the following conclusions:

Ideal Model






The loop gain has a large variation depending on the current range. This is not desirable.

Darlington Transistor Gain

The current gain of the Darlington Transistor falls with lower currents:



In this applications, this reduction in gain at low currents helps.

If I reintroduce the Darlington transistor and measure the loop response I get:





You can see how the gain is compressed at low current by the Darlington transistor.


To be continued ….

Regards,

Jay_Diddy_B

[Jay_Diddy_B]

Opamp

If I reintroduce the opamp. I am using the LTC2050 that is included with the LTspice library:





The LTC2050 is sufficient close to an ideal opamp in this application that it does not have any impact in the loop gain.

To be continued …

Regards,
Jay_Diddy_B

[Jay_Diddy_B]

MOSFET Switches

Only the MOSFET switches are left.

When the MOSFET switches are off, the parasitic component is dominated by Coss. Coss is the output capacitance:



If I build a simple AC model to explore Coss I get:






This is a single pole at 1kHz.

C= 1/(2 x pi x F x R)

C= 1.6nF

Coss = 1.6nF

This matches the Coss from the Si4412DY datasheet:



To be continued …

Regards,

Jay_Diddy_B

[Jay_Diddy_B]

Coss

If I replace the ideal switches with a short or capacitor on the 1A range I get this:





This is a major deviation from the ideal result. The Coss has a large impact on the loop gain.
I have only added the Coss for the low current switch. If I add all the capacitors I get:






There is very little difference.

Observation

The Coss of the MOSFETs on the low current range is the most important.

To be continued ...

Regards,
Jay_Diddy_B

[Jay_Diddy_B]

Smaller MOSFET

If I select small MOSFETs, higher RDS_on, but smaller C_oss on the lower current ranges I can get better performance from the circuit.





The Coss of the 2N7002 MOSFET is 100pF

If I use these MOSFETs for the lower current ranges, I get:






This is a good result. The circuit is very well behaved on all the current ranges.


I have attached the LTspice model.

Regards,

Jay_Diddy_B

[OM222O]

the element by element analysis was extremely useful!

From now on I don't think I'll have any issues with my designs since I learned a lot from this thread!
Thank you all for explaining it in such details and saving my butt!