current and slave select pins

[joniengr081]

I am using this "SC18IS606" I2C-bus to SPI bridge chip in the circuit.

The datasheet is available under the link below.
https://www.nxp.com/docs/en/data-sheet/SC18IS606.pdf

I understand the address pins A0, A1, A2. I can have eight chips on one I2C bus with eight unique address set by address pins A0, A1, A2. I will connect these pins to VDD or GND accordingly.

I am not sure about how do I connect the following pins in the circuit.
SS0/GPIO0
SS1/GPIO1
SS2/GPIO2

I am not using these pins as GPIO.

Last question is what is the current consumption of this chip ? I am wondering about the power supply current.

[magic]

Wild guess without RTFM: aren't you supposed to connect these pins with CS pins of your SPI slaves?

I presume you can toggle them with I2C commands, to choose which slave will respond to the subsequent SPI bus transaction.

[joniengr081]

I think it is like that as you said.

The slave select pins ( SS0, SS1, SS2) are three output pins that need to be connected to the CS pin on each SPI device. But does it means that we can connect only three slave SPI chips with one "SC18IS606" ?

The SPI master will determine or select which peripheral IC to talk with.

[Siwastaja]

The slave select pins ( SS0, SS1, SS2) are three output pins that need to be connected to the CS pin on each SPI device. But does it means that we can connect only three slave SPI chips with one "SC18IS606" ?

That seems like a reasonable limitation. In real world designs SPI is often just point-to-point between two devices. One master + three slaves is quite advanced case already, if you want more it's not a bad idea to build more buses, i.e. get more of those I2C-to-SPI bridges. If you then run out I2C addresses it isn't a bad idea to increase number of I2C buses, too.

But if you must have more than three, but seven suffices, then easiest way to extend this capability from 3 to 7 slaves is to use 3-to-8 demultiplexer IC, so that the bit patterns on SS signals map to one-hot outputs, i.e. 000 = all inactive, 001 = first slave active, 010 = second active, 011 = third active, 100 = fourth, 101 fifth 110 sixth and 111 seventh active. So basically a standard 3-to-8 demux with first output (000 case) unconnected and rest 7 outputs driving the slave selects. I don't offhand remember part numbers if some with the active-low output polarity is available, or if you need to add inverter stage afterwards. Open-collector outputs with pull-ups would of course do the same.

All this begs for the question, what you are actually building? How many SPI devices you are dealing with and why so many? 8*3 is already 24 controllable SPI devices through a single I2C bus, and if you do the demux trick then it's 8*7 = 56.

[eutectique]

But does it means that we can connect only three slave SPI chips with one "SC18IS606" ?

If you want SPI slaves to be selected by the bridge, then yes, three slaves (Table 4).

You can set SS0 as GPIO, and SS1 and SS2 as slave selects. This way two slaves will be automagically controlled by the bridge (commands 0x02 and 0x04). You will then control other slaves by your MCU and send command 0x01 to the bridge.

[eutectique]

As per current consumption, Table 13 "Static characteristics", the line I_DD(oper). Take into account pin currents in Table 12 "Limiting values".

[joniengr081]

I get the static current from Table 13.

But how can I add or get the current from Table 12 ?

I have highlighted the three rows in Table 12 in attachment.

I am not using GPIO0, GPIO1, and GPIO2.

Only one SPI slave is connected to SC18IS606.

The SS0 pin of the SC18IS606 is connected to CS of the slave SPI.
The MISO pin of the SC18IS606  is connected to SDO of the slave SPI.
The MOSI pin of the SC18IS606  is connected to SDI of the slave SPI. 
The SPICLK pin of the SC18IS606  is connected to SCLK of the slave SPI. 

The address pins A0, A1, A2 of the the SC18IS606 are connected either to VDD and or to GND.
The SDA and SCL pins pins of the the SC18IS606 are connected to host MCU.

How do I calculate the power supply current ?

[Nominal Animal]

The most common jellybean option to expand those three slave select bits to seven, assuming standard /SS active low logic, I believe is 74xx138, say NXP 74LVC138A or NXP 74LV138.  If board area is an issue, I'd consider TI SN74LV138A in 16-WFQN (SN74LV138ABQB, 3.6mm × 2.6mm) or BGA (SN74LV138ANSA, 2mm × 2mm).  All of them have a particularly nice layout if you only need six /SS outputs, leaving Y7 floating.

Annoyingly, the SS0, SS1, SS2 outputs would need to be inverted to map the unused command (0x00) to Y7, to get seven slave selects.  You can easily do that with say a NXP 74HC3G14 (or any other 74xx3G14), or with any jellybean hex inverters (one for a pair of '138s).  That way, command 0x01 would enable (pull low) Y6, 0x02 Y5, 0x03 Y4, 0x04 Y3, 0x03 Y2, 0x02 Y1, and 0x01 Y0.  This is particularly nice, because Y7 is on the address/enable side of the IC, so leaving it the unused one makes for a very clean PCB layout in my opinion.

(Note: I'm only a hobbyist, with a few simple PCB designs, not ready for BGA yet.)

For the current, I read max. 4mA plus the current is sourced or sunk on the outputs (SS0, MOSI, SPICLK, SDA on ACK/NAK).  The output currents vary too much –– for example, sometimes very small resistors are added in series to increase the current and the power needed for coupled noise to affect the signals –– to give a reasonable estimate; but if connected directly to a CMOS IC, it would be neglible, less than a milliamps or so (in the tens of microamps range in steady state, maybe a few hundred microamps when changing state).

One "trick" I like to do is a TI TXU0304 or TXU0304-Q1 at the peripheral-facing end, to allow for both voltage level translation (if needed) and to move the current draw from the MCU or FPGA to the TXU0304 chip.  (I also use TI ISO7741 for both SPI isolation and level translation, when I don't know exactly what I shall be interfacing to, making it easier for me to avoid current loops and such in my designs.  But more experienced members here have tried to convince me using isolators that way is poor design, so beware.)

[Siwastaja]

But how can I add or get the current from Table 12 ?

The table lists how much current you are allowed to draw from these pins. Only you can know how much you do. If you use them to control normal CMOS ICs, like you probably do, then it's very close to zero, unless you add some pull-up resistors in an attempt to maintain some safe default state, then current will flow: Iavg = D * Vcc/R, where D is the duty cycle (chip select active time per total time) and R is your pull-up resistor value.

[joniengr081]

If I use 5 mA current for one SC18IS606. Would that be ok to count 5 mA as power supply current. ?
And if I have eight chips connected on the same I2C then the total current which I am counting is 5 mA x 8 = 40 mA.

But then I am thinking, only one chip will be active or working at a time, and not all.

Let's say all of them are working.

How about if I take 40 mA as power supply current for eight SC18IS606 ?

[Siwastaja]

But then I am thinking, only one chip will be active or working at a time, and not all.

The datasheet helpfully specifies lower current for "idle mode", but you have to use a separate command to enter the idle mode. With reduction from 4.0mA(worst) to just 3.4mA(worst), this doesn't seem to have much effect and I would not probably bother with using the idle mode for small saving like this. Therefore it would be simple to calculate static operating current as 8 * 4mA.

If you use high data rates then any dynamic power consumption is not included and is difficult enough to calculate that a prototype measurement is probably a good idea. But unless you are maxing out the capability of those chips (highest SPI clock rates, nearly non-stop packets), I'm quite confident your 5mA per chip is a safe estimate. Especially if only one is active at a time.