Creating synthesized sine wave with PWM, with no DC bias current in transformer

[hkBattousai]

I'm designing a sine wave output inverter. In classical method, you know, you generate a high frequency PWM signal, and duty cycle of this PWM carries the information of amplitude of the sine wave you want to generate. And you drive your transformer by a H-bridge.

But there is a problem in this design. If the duty cycle of the PWM is something other than D=0.5, DC bias occurs in the primary winding of the transformer. This causes very high flux density in the transformer core, so you have to use huge cores to avoid core saturation.

I have found out a circuit model which will overcome this problem. It is my own design. I don't know if it was done by someone else before, or it is used in practical circuits. But I have never seen it anywhere before. I need approval/criticism of it from the expert users in this forum.

Here is the block diagram:

I think the block diagram is self explanatory. Ask any details about it under this topic if you need.

And here is the signal timings I am planning to get:


What do you think about this method? Would it work successfully and do what it is supposed to? Will this help me use a smaller transformer core in my design? Please leave some comments about it and make me suggestions.

[dannyf]

Creating synthesized sine wave with PWM, with no DC bias current in transformer

complementary pwm output + center tapped transformer.

[pipe]

Looks like the pulse-skipping done by some switch mode regulator circuits.

Is the DC offset actually a problem over such a short time, when you alternate between a positive and negative offset as you do with a sine wave?

[hkBattousai]

Looks like the pulse-skipping done by some switch mode regulator circuits.

Is the DC offset actually a problem over such a short time, when you alternate between a positive and negative offset as you do with a sine wave?

If I had directly applied the PWM signal to the primary winding, as it is done in the ordinary way, the frequency of the PWM would have been very high (e.g.; 100kHz-->10us). For example, when generating the high side of the 50Hz sine wave, a positive PWM signal squence will be applied for the entire 10ms (1000 times higher than the period of PWM). Even during the logic-low state of the PWM, there still will be current flowing through the primary winding of the transformer over the body diodes of the H-bride MOSFETs. In other words, the primary winding will act as an RL low pass filter and filter the PWM wave to some residual DC current (+ tiny ripples from the PWM). This residual DC current is the DC bias itself I am talking about. Because of this DC bias, the magnetizing current (I_m) of the transformer becomes excessively high. And because of this high DC bias current, high magnetic field density occurs in the core and saturates it. And, in order to prevent core saturation, I have to use huge transformer cores (e.g.; Epcos E70 barely suffices) for a 2kVA device. But if I apply this new method, according to my calculations, an incredibly much smaller core will be enough (but still I will be using a slightly larger core because of other kinds of losses).

I know that my method will make very high ripples at the output sine wave because of the low frequency (1kHz) PWM signal. Hardness of filtering it will be a side effect.