How to even start routing this?

[Joanna_H]

Nice thing about the XO2 is it has onboard config memory, core voltage regulator and also an oscilllator, so minimal extra parts. A few package options from QFN32 to QFP144.

Yeah, like the QFP144, enough I/O to get things going..   as I'm trying to create a "modular" cpu that you can see what each bit is doing this could be a nice path.   But I think I'll need a few of them as I'll need quite a few control lines.  Even so, it's worth exploring as an option    

[NivagSwerdna]

I was trying not to mention FPGA as it seemed to go against your design goals and I was assuming this was a 5V retro project.  Checkout TinyFPGA for design ideas if you are going that route.

Mike has replied and has a lot more experience than me but XO2 does come in small configurations or there is ICE40.

Have fun

[rstofer]

Back to routing:

If any of the devices are memory chips, you don't have to keep strict alignment between A0->A0, A1->A1, etc.  You can hook the address lines in any sequence.  The only thing that happens is that logically adjacent address are spread around in the memory.

Same deal for data lines.  D0 doesn't have to be right next to D1.

This turns out to be a real big deal when working with memory and MCUs.

ETA:  This may cause problems with DDR memory but is often used for SRAM.

[Joanna_H]

I was trying not to mention FPGA as it seemed to go against your design goals and I was assuming this was a 5V retro project.  Checkout TinyFPGA for design ideas if you are going that route.

Mike has replied and has a lot more experience than me but XO2 does come in small configurations or there is ICE40.

Have fun

Yeah, my original goal was all TTL, but with board space, number of components, etc. etc..  The cost would become silly.

[Joanna_H]

Thanks for the FPGA suggestion, this is fun.   Different way of thinking about it all, but I should be able to achieve the same goal.   A CPU that you can monitor every part of it and see how it works

Thanks.

Verilog is a bit interesting though.......   Something new to learn.

Still, having fun..   AddressLineDriver / Program Counter and a few other bits done so far.   



The second jump test is an inpage jumping test, which gives a data bus size jump range (16bit in this example) costing only 1 cycle.

[Joanna_H]

You know the world has become a little scary when you can fit the majority of an old school 16bit processor into about 2% of a low spec FGPA.......

LCMXO2-640UHC-4TG144C. had to choose the 640 as the lower one doesn't have enough I/O pins :/



I'll post no more on this in this thread as I've gone way of topic now.

[SiliconWizard]

You know the world has become a little scary when you can fit the majority of an old school 16bit processor into about 2% of a low spec FGPA.......

Not surprised.

You did that pretty fast!

[PlainName]

Just like to say that a good habit to develop is to keep pin1 in the same orientation for all chips. Sometimes it's not practical but in that case keeping complete groups the same is a reasonable fallback. Similarly, diodes all point the same way (for those all pointing up/down or left/right). The reasoning is to prevent assembly cockups.

[Joanna_H]

Woops, just noticed I was up all night messing with this.. LOL

Still, have some things now working.

A simple test of a NOP, JMP (in page, LSB only) and LJMP (anywhere in memory, uses both MSB and LSB) was fun.  But starting to eat up those resources as I add more stuff

At least the microcode isn't on the FPGA, seperate EEPROM to allow for easy program/reprogram of that little part.  Both memory and eeprom simulated in the testing to see how it's going