How do extract parasitic inductance in a power mosfet (PWM/SMPS design)

[Fusion916]

Hi all,

I kind of got caught with my pants down not modeling the parasitic inductance on the PWM drive line (both layout/routing inductance and parasitic from power mosfet). I can figure out how to model the layout parasitic, but is there any way to extract and model the parasitic inductance inside a power mosfet package from the datasheet? Or is there anyway to make an educated guess given the device package or given parasitic capacitance?

[jbb]

There is a way to extract it, but I suspect it's pretty difficult.  First up, does your data sheet have anything to say about it?
Second, does the manufacturer offer a SPICE or SABRE model for it?

Typically the source leakage inductance is the most critical.

[T3sl4co1l]

Are you okay with typical values for various package types?

For example, TO-220 inserted to full depth (i.e. up to the shoulders on the pins) is about 5nH per pin.

Tim