Comparator for restoring 27MHz clock from sine signal.

[Esmund]

Hello,

I'm looking for comparator that allowes me to restore 27MHz clock from sinusoidal waveform ( min. 100mVpp ). I'm struggling with finding one because it's low power solution, so maximum quiescent current suppose to be around 1mA, and minimum supply voltage around 2V7 / 3V0. Are you familiar with any solution that meets the requirements? Thank you for any help.

Best regards,

Esmund

[Benta]

With those requirements, it might be easier to build a discrete amplifier/clipper.

[OwO]

PL133-37 at 2.5V seems to meet those specs

[DaJMasta]

I assume this is a sine centered around zero?  Well if it's just a sine, you already have your clock, you just have to make it usable by digital circuits, so:

signal -> DC blocking cap -> resistor divider to bias the signal to remain positive -> schmitt trigger/transistor amplifier/fast comparator -> regular, sharp edged digital clock signal


Since you already have the signal in a clean state, the basic approach, as mentioned in the second post, is to amplify it - this will get you a more-square edge in the voltage range of interest, but then clip off the top and bottom.


Worth mentioning, a pure sine wave is generally the clock of choice at high frequencies, and is sometimes most of what is manageable when the parasitics start rounding the edges of your square wave.

[LapTop006]

I'm looking for comparator that allowes me to restore 27MHz clock from sinusoidal waveform ( min. 100mVpp ). I'm struggling with finding one because it's low power solution, so maximum quiescent current suppose to be around 1mA, and minimum supply voltage around 2V7 / 3V0. Are you familiar with any solution that meets the requirements? Thank you for any help.

For this purpose I quite like the Linear Tech LTC6957, although it (the CMOS output version at least) uses ~20x more power than you want.

[floobydust]

Relevant thread: https://www.eevblog.com/forum/projects/level-translate-the-output-of-a-tcxo-crystal-oscillator-module/

[Zero999]

I assume this is a sine centered around zero?  Well if it's just a sine, you already have your clock, you just have to make it usable by digital circuits, so:

signal -> DC blocking cap -> resistor divider to bias the signal to remain positive -> schmitt trigger/transistor amplifier/fast comparator -> regular, sharp edged digital clock signal

Yes, a couple of logic gates with feedback resistors will do that.

[SteveyG]

How much jitter and hysteresis can you tolerate? Do you care about the phase shift?

[Esmund]

At first, thank you for all responses. It's superb how many people are willing to help, but going back to topic...

With those requirements, it might be easier to build a discrete amplifier/clipper.

I'm trying to avoid such a solution for now, but if I'll have to I'll probably will test it, if it necessary.

PL133-37 at 2.5V seems to meet those specs

Something like that IC would be nice, however I can't see input high/low voltage levels at datasheet, but anyway that may be IC to take into consideration to test.

signal -> DC blocking cap -> resistor divider to bias the signal to remain positive -> schmitt trigger/transistor amplifier/fast comparator -> regular, sharp edged digital clock signal

That's exactly solution I'm trying to implement, issue is to have low power amplifier with such a bandwith.

For this purpose I quite like the Linear Tech LTC6957, although it (the CMOS output version at least) uses ~20x more power than you want.

Unfortunately, I can't afford to use so much current for one IC.

Relevant thread: https://www.eevblog.com/forum/projects/level-translate-the-output-of-a-tcxo-crystal-oscillator-module/

I think about trying transistor-based amplifier, it may be suitable for that application.

I assume this is a sine centered around zero?  Well if it's just a sine, you already have your clock, you just have to make it usable by digital circuits, so:

signal -> DC blocking cap -> resistor divider to bias the signal to remain positive -> schmitt trigger/transistor amplifier/fast comparator -> regular, sharp edged digital clock signal

Yes, a couple of logic gates with feedback resistors will do that.

How about low input amplitude? I believe all logic gates like that have built in hysteresis loop, so I believe it won't be able to switch.

How much jitter and hysteresis can you tolerate? Do you care about the phase shift?

Hysteresis at input? I'd like to keep it low because of low peak-to-peak input voltage. Phase shift is not an issue. Do you mean jitter at input? If so, I think it can be not taken under consideration for now.

[OwO]

Something like that IC would be nice, however I can't see input high/low voltage levels at datasheet, but anyway that may be IC to take into consideration to test.

There are no input high/low voltages because it's internally AC coupled. There is a "Input (FIN) Signal Amplitude" on page 3 which is minimum 0.1V peak to peak at <40MHz.

[Zero999]

I assume this is a sine centered around zero?  Well if it's just a sine, you already have your clock, you just have to make it usable by digital circuits, so:

signal -> DC blocking cap -> resistor divider to bias the signal to remain positive -> schmitt trigger/transistor amplifier/fast comparator -> regular, sharp edged digital clock signal

Yes, a couple of logic gates with feedback resistors will do that.

How about low input amplitude? I believe all logic gates like that have built in hysteresis loop, so I believe it won't be able to switch.

Ordinary logic inverters such as the 74AC04 don't have any built-in hysteresis loop, so it should work perfectly at low input amplitudes. A single non-inverting gate could be used but I suggested two inverting in series, simply because they're more common.

Here's an application note which goes through the calculations.
https://www.parallax.com/sites/default/files/downloads/AN015-SchmittTrigger-v1.0.pdf

Another useful link:
http://solarbotics.net/bftgu/tutorials_schmitt.html

[Ian.M]

Doesn't the first inverter need negative feedback to keep it near its switching point?

Lets assume the output of the second one has railed (maybe transiently during startup).  Best case: the input cap will have charged so the first input is biased all the way to the same rail within 50us, and worst case could be under 20us.  Once the input's at the rail, a 100mv pk-pk input signal wont get it far enough off the rail to switch. Heck, assuming 80% logic '1' and 20% logic '0' thresholds, it wont even get it out of a valid logic '1' or '0' level!

[iMo]

I was using this shaper with my reciprocal counter, and it worked nice (5/10MHz in my case).
The L1C1 at the input is tuned to the frequency, 27MHz in your case.
That amplifies the input sine, up to 4-5Vpp at the node "A" when lucky (because of the LC in resonance), moreover, it should lower the jitter as well.
After that LC a faster AHC14/AHC04 inverter could be used (ie the 5pin smd part).
The R2/R3 resistors create bias in the middle of the AHC14 schmitt-trigger range. The AHC04 should work as well.
The signal source should be low impedance.
Not tested in hw at 27MHz.

[Zero999]

Doesn't the first inverter need negative feedback to keep it near its switching point?

Lets assume the output of the second one has railed (maybe transiently during startup).  Best case: the input cap will have charged so the first input is biased all the way to the same rail within 50us, and worst case could be under 20us.  Once the input's at the rail, a 100mv pk-pk input signal wont get it far enough off the rail to switch. Heck, assuming 80% logic '1' and 20% logic '0' thresholds, it wont even get it out of a valid logic '1' or '0' level!

You're right. 

I'm used to building this circuit with an input which is biased at approximately half the supply voltage. Anyway, this won't work with buffered gates. You need the unbuffered variety, otherwise adding negative feedback in the manner you've described, results in an oscillator. The supply current will also be very high. It's a bad idea.

[Ian.M]

You're right. 

I'm used to building this circuit with an input which is biased at approximately half the supply voltage. Anyway, this won't work with buffered gates. You need the unbuffered variety, otherwise adding negative feedback in the manner you've described, results in an oscillator.

That needn't be a problem.  As long as the frequency of free oscillation is much lower than the input frequency, it will sweep the input bias through the switching point and lock onto the input frequency.  Depending on the time constants in the feedback loop it may take a time equivalent to a period or two of the free oscillation to stabilise.  See attached sim.  Whether or not you need to add extra logic to suppress the output till its locked to the input frequency depends on the application.

The supply current will also be very high. It's a bad idea.

Maybe, but  as supply current for logic gates in transition is poorly specified - if at all - you wont know for certain till you suck it and see.

I agree its a lousy idea for production, unless you are prepared to qualify each batch of inverters for satisfactory operation and low enough supply current, but its entirely usable for one-offs and prototying - until you can get a more suitable fast comparator or limitng amplifier.

[OwO]

Why deal with all these hacks when a PL133-37TC costs $0.5 and can accept 100mV peak to peak input  Really reminds me of that "unnecessary complexity" thread someone mentioned "baroque designs" 

[nick_d]

Can this do it?
http://www.ti.com/product/SN74LVC1G14

The qiuescent current is 10uA, would have to check power draw from switching based on your input frequency and so on.

The amount of hysteresis at 3V (the difference in input thresholds) can be between about 0.4V and 1.0V. Thus you would want an input sine wave of at least 1V (plus margin) peak to peak.

Do you actually need the high pass filter and centre-ing circuit? If so then I suggest to bias the input with a resistive divider, say 1M to +3V and 1M to ground. Biasing it with feedback may be problematic as has been mentioned.

If the input frequency is going to be high enough you won't need the Schmitt and could go for this one:
http://www.ti.com/product/SN74LVC1G04
That would allow a much smaller peak to peak input, if you can bias it accurately.

Finally, whatever you are driving with this clock signal might be able to handle the sine wave input directly, check it!

Edit: whoops just noticed the 100mV peak to peak specification. Yes that would be problematic for the 74LVC1G04 solution. Back to the drawing board. New idea: what about a comparator that compares the signal with the RC filtered low passed version of the signal? Set cutoff to somewhat lower than 27 MHz. Use a slow enough comparator that no hysteresis is needed, the slower slew rate would save power too. The only tricky part is most comparators have open collector output, and the pull-up will waste power.

cheers, Nick

[Esmund]

Ok, thank you for all responses. I'll design PCB to test some of concepts that you gave me here. I'll share my results as soon as I finish, maybe it'll be useful for someone else . To be honest I really like idea to use PL133-37TC, I missed at first that ac coupled input operates from 0.1V.