PCB layout: Vias in clock traces

[ebastler]

I am working on an SMD design where I won't be able to fully route the clock traces on the component side. I am wondering -- what is the best (least bad) way of routing part of the clocks on the back side using vias? Please see the attached illustration:

• (A) Minimize the use of vias. Route the clock on the top layer where possible, connect the actual clocked chips directly to traces running on the top. Only dive to the bottom layer a couple of times where the connection can't otherwise be made.
• (B) Keep one uninterrupted clock line on the bottom layer, using a via and very short tap to each clocked device.

I am leaning towards (B), reasoning that the short taps can be largely neglected from a transmission line perspective, and that one does not want vias (with their impedance jumps) along the main clock line. But I could be totally wrong here. Thanks for your comments!

Additional context: This will be a 74HC design, hence modest rise times of several ns. So I hope it won't be overly critical, but since the clock traces can get longish (~ 30 cm), I don't want to create avoidable problems. I plan to use a few clock drivers in parallel, but nevertheless can't get the clock to all recipients using the top layer only. Clock lines will be terminated at the far end.

More context: Hobby project, amateur at work. (As you can probably tell from the question.) 

[spostma]

I would choose option B; so run the clock line uninterrupted over a continuous ground plane,
and have small stubs to chips on the other side.

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Regarding termination; I would only use 33R series termination directly at the output of the driver, and not at the far end.
Thus the incoming wave will have VCC/2 amplitude, reach 100% ampliture when bouncing at the far end,
and be absorbed at the series terminator when travelling back to the driver output.
This is the termination scheme the the classic PCI bus uses.

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A trace that is terminated with characteristic impedance running over a ground plane gives almost no emissions
as long as it does not run near the edge of the ground plane!

[ebastler]

Thank you -- a first vote for option B, that's reassuring!

Regarding termination; I would only use 33R series termination directly at the output of the driver, and not at the far end.
Thus the incoming wave will have VCC/2 amplitude, reach 100% ampliture when bouncing at the far end,
and be absorbed at the series terminator when travelling back to the driver output.
This is the termination scheme the the classic PCI bus uses.

But isn't that serial termination limited to the situation with only one receiver per clock line, which sits at the end of the trace? Any additional receivers placed along the way will first see the VCC/2 level only, then jumping up to full VCC a bit later when the reflection comes back. That sounds very undesirable...

[T3sl4co1l]

(C) Whatever's easiest to route.

Clocking what?  Like just SPI stuff or something?

I'd probably favor a conditional layout, for which I'd need to see what all is involved.

30cm is not quite a full 74HC edge, so it's in the regime where some care is warranted, but no need to go crazy with it.  Little more than a source terminator, and some observation of similar routing/timing against whatever bus this is clocking, will be fine.  The whole thing could be stubs and you probably won't notice.

Tim

[ebastler]

Thanks, I'm happy to go with "easiest". Maybe I am overthinking this. I'll give a bit more background:

What I am putting together is a vintag-y computer design: A demonstrator for the Pilot ACE (designed by Turing in 1945, eventually realized in 1950). I am using real ultrasound delay line memory and the same architecture as in the original ACE, but have scaled the memory size and word length down a bit and am using 74HC logic instead of the original 700+ tubes. Yes, it's a bit of a strange crossbreed of "Alan Turing meets the KIM-1", but at least the 74HC series and the PAL TV chroma delay lines are of similar vintage...

Anyway, that means approx. sixty 74HC chips -- a lot of them flip-flops and shift registers, clocked synchronously. Parts placement is to some extent determined by the desire to make the computer architecture visible, as a kind of "working block diagram". This results in distances which are sometimes larger than techically needed, and in less-than-ideal clock routing. I need to clock about 40 chips, and intend to group them in five clock nets with separate drivers. So each clock net will need to serve between 5 and 10 clocked chips.

You mention source-side termination too. Same question as above: Assuming that means series termination, does this really work for multiple listeners on the clock line? -- Oh, and what is a conditional layout? I do't think I have come across that term. Thank you!

[T3sl4co1l]

Ah, neat.

Yeah, more important is just good grounding, as long as it has a solid ground plane you can get away with a lot of messy routing.

The pin loads are small and capacitive.  To some extent they are served by the trace inductance itself (though ideally this should be a coupled inductor to do that -- it would make an all-pass filter), and ultimately, the pin driver resistance, and whatever external resistance is in series with it.

Also interesting is that, for loads midway along the route, a half-step waveform is seen; this is characteristic of source termination.  On a long route, this might be disastrous, but again, as hardly a switching edge passes along the full length of a 30cm route at any given time, it's not going to be a big deal.  (Schmitt trigger receivers may be desirable.)  It is something to think about for longer routes.

Also, if this runs rather slowly, there's not much wrong with simply slowing the edge rate, within reason.  Clocked devices ('74 flip-flops, etc.) don't like super slow clock edges, but they also give a tolerance for what counts as slow.  As long as you are within those limits, you're good.  And the edge rate can be slowed simply by increasing the series resistor above its ideal value, so that the trace effectively gets charged as an RC network (it's actually the accumulation of several wavefronts reflecting back and forth, building up, if you look at it as a transmission line; in the low frequency limit, these are equivalent).  This prevents ringing on the trace, at least from the driving source, but there are plenty of other ways to get noise into things -- which again is why good grounding is important.


By "conditional", I simply mean, I would have to see the circumstance and make a decision based on that.

Tim

[ebastler]

I did a quick experiment, driving a 40 cm coax stub with a 74HC output. An indeed, series termination on the driver side works much better:

The limited drive strength of the 74HC output does not allow a correct parallel termination, even with split, Thevenin-style termination resistors. 2*680 Ohm already reduce the signal swing noticeable and are still pretty ineffective as a termination. On the other hand, series termination with 39 to 56 Ohm gives a clean clock signal at the far end of the coax, and the half-voltage step at the near end is evened out nicely by the limited slew rate of the output.

Thanks for the tip, I would not have thought of series termination with multiple receivers on the clock line.

[T3sl4co1l]

Load termination works if you can afford the transmitter power, and have receivers suitable for the reduced signal level.  74HC7014 is an excellent example.  Its threshold is slightly above midpoint (around 60% I think?), so dimension the (divider) termination resistors accordingly.  Unfortunately, your average CMOS inputs (30-70% threshold) aren't compatible.

Heh, I suppose Ye Olde TTL inputs would be compatible, though.  And HCT in turn.

Also, a higher impedance medium helps, so this works better for narrow PCB traces and ribbon cables (Zo ~ 120 ohm) than for driving coax, or multiple loads.

Tim