Minor gripe: TI's TPS54226 switching regulator. There's an Enable pin, and a Vreg pin that supplies 5v for control circuitry. The Enable pin is diagonally opposite from the Vcc pin (with a ground pad between) but in my layout, the Vreg pin was fairly easily accessible, so I thought "OK, I'll tie Enable to Vreg". Predictably, it turns out Vreg is ALSO disabled when Enable is LOW, so my prototype board had a bit of a chicken and egg thing going on.
To be fair, I realized this was a possibility, and combed through the datasheet looking for confirmation one way or another -- and therein lies my chief complaint. There isn't one word about this either way. In the block diagram, Enable goes to a single isolated block labelled "Enable Logic". In the application circuits, Enable goes to an external header. In the timing diagrams, the sequencing is shown between Enable, Vout, and PowerGood, but not Vreg. In the text, not even a single paragraph is devoted to Enable's function.
For an essential (albeit trivial) signal, there's not much attention given to how it works.