Class E Power Amplifier Questions

[promach]

I have some questions about Class E Power Amplifier

1) From page 183 of Advances in Electronics, Communication and Computing ,

(a) why Maximum output power is calculated as 0.577 Vdd² / R ?

(b) What does it mean by Vgs (min) = 5% of Vdd = 0.09 V and Vgs (max) = 7% of Vdd = 0.126 V. Therefore Vgs value will be in between 0.09 and 0.126 V ?




2) From Figures 4 and 5 on page 3 of A Class-E RF Power Amplifier with a Novel Matching Network for High-Efficiency Dynamic Load Modulation ,

(a) how to determines values of all the values of capacitors and inductors of both the input and output impedance matching networks ?

(b) how to use LTspice to simulate if it does not have smith chart plotting capability ?

(c) How to bias the two pull-up inductors (Lrf, Ldriver) and two resistors (Rb1, Rb2) ?

(d) How does the proposed digitally-controller matching network works ?

[trobbins]

Is this for course work that you are meant to do by yourself?

The first query relates to the energy transferred through the class E Vds waveform if I recall correctly (that waveform is a specific shape to achieve the class E ZVS conditions).

The second query seems to relate to the nMOS fabrication process - are you fabricating parts or using COTS?

The second set of queries - now I see the basis for your queries from the referenced paper.  You need to do your homework on class E - there are lots of papers going back to the late 1970's that go through the basics - the early ones are all based on lumped parameters, as that was when discrete power FETs restricted operating frequencies to pretty much less than a few MHz.  The proposed technique to modulate the C values in alignment with the class E switching frequency, in order to modulate the output seems interesting.

[TheUnnamedNewbie]

I'll focus on part 2, it's been a while since I've looked at CMOS class E amplifiers.
What the authors do in this case is take an IQ signal from the source, and split it up into a CW signal with phase modulation, which they amplifier. To get back amplitude control, they tune the matching network efficiency to change how well the amplifier manages to get power back to the load.

2a) You would probably do some kind of load-pull to figure out the impedance, and then determine the optimal load impedance for efficiency. They will simulate a range of matching networks they can use, but probably also just use a kind of calibration to tune the optimal combinations of matching networks to get the performance they want.

2b) No clue, LTSpice is just not made for this kind of application. You'd really want to do some kind of PSS/loadpull simulation in SpectreRF/ADS/MWO.

2c) What do you mean 'bias the inductors'? You just slap on a big capacitor at the other end to make an ideal RF short there, and hook up VDD.

2d) Read the paper.

[promach]

How exactly to "do some kind of load-pull to figure out the impedance, and then determine the optimal load impedance for efficiency" ?

What do you exactly mean by "just slap on a big capacitor at the other end to make an ideal RF short there" ?

[TheUnnamedNewbie]

When you perform a load pull, you connect various complex loads to an amplifier output (either in reality using a load-pull setup, or in a simulation like non-linear periodic steady-state analysis). Then the output power is plotted on the smith chart. Usually people will draw 'circles' connecting the point that have the same output power, or efficiency, or some other performance metric.

The reason this is done and can't just be computed from some static S-parameters is because the non-linearity of an amplifier modulate the impedance it presents. This means that depending on the signal level, the ideal output match is different (which is why load-modulation is a common way to improve efficiency).

In this case, the authors would need to know what output power is produced by different output impedances, so they can use this output-match as a output-power modulation technique.

With the 'slap on a big capacitor', I meant that for an RF amp, you usually start with a good low-impedance supply line - which is equivalent with a short at your frequency. You create such a low impedance by having a local decoupling capacitor on chip. You add an inductor between the supply and the PA transistors to tune out the capacitance of the gate (in a sense it forms of your matching network).

[promach]

Why is the following PA circuit not working ?

[SiliconWizard]

Well, first thought from a quick look: you're driving it with a 1 MHz signal - and looking at the L and C values, I very highly doubt your class E amp is tuned for 1 MHz.

[promach]

you're driving it with a 1 MHz signal - and looking at the L and C values, I very highly doubt your class E amp is tuned for 1 MHz.

I am not good at RF impedance matching, would you be able to give some comments on the LC values tuning ?

I understand that both the T and pi impedance LC networks need to be tuned.

I Iooked at Nathan Sokal original document about class-E power amplifier : Class-E High-Efficiency RF/Microwave Power Amplifiers: Principles of Operation, Design Procedures, and Experimental Verification

but there is not much information about RF impedance tuning

Besides, there are also parasitic capacitance arising from the two NMOS mosfets.

How do I use ".net Vin I(R3)" to do impedance matching inside LTSpice ?

[trobbins]

Pretty much all those simulation component values are meant for a much higher frequency operation than 1MHz.  Where did you get the simulation parameter values from?

As an aside, have you prepared yourself for attempting this type of project/assignment - I would have though this would require at least a basic electronics/electrical engineering degree level of awareness of impedance and frequency and networks and simulation tools.