Hi there,
Well, I realized once again that electronic design is pretty hard as almost every component characteristic depends on so many things.
Yes, many things; but only finitely many, and not just finite, but just a few components, in most cases. So it takes a lot of practice to get used to them, but in the end it's not a big burden.
Right now I’m looking on the characteristics for a ceramic capacitor to use for the output capacitor in a fast synchronous buck regulator. To me the best capacitor to select is the one that has it’s self-resonance (lowest impedance) right at the frequency where the main frequency content is of the signal that you want to filter out. Correct me if I’m wrong at this. If it is correct I consider it very odd that I haven’t found this statement in all the appnotes and whitepapers, and some books I’ve read.
Now, keep in mind this isn't so much a characteristic of the component, as simply its physical length.
And you don't simply have a component in isolation. You have to connect to it with traces, and those traces have length!
Indeed, a typical capacitor might have a mere 0.8nH in published data, but this is normalized to the inside edges of the pads it lies upon.
The SRF is not so much a property of the component, but that of the component in a particular system.
So the value of SRF for capacitors is not great. The inductance is part of your circuit. You can't get it lower than the published data, but beyond that, it is not an assumed characteristic, but your responsibility, a design parameter under your control.
So, do you know any application notes or other guideline to properly estimate the self-resonant frequency in specific circuit conditions like the applied DC voltage and temperature but also considering capacitance tolerance?
Better to take a step back and consider what the ESL is doing.
At very high frequencies, Xc ~= 0, and X_L > ESR, so we can model the capacitor as an inductor.
We are supplying this inductor, from an AC source (square wave), through another inductor*, so we have an inductor divider. The ratio of inductances gives the attenuation factor.
*Except we need to use a high frequency model here too, of course, which will be some awkward capacitance and resistance, not a pure inductance.
For low output noise, we want ESL --> 0. This is impossible, so we should merely reduce it as much as
practicable, and if more filtering is required, follow on with another LC stage (which can be smaller values than the first LC; smaller values --> higher SRFs --> better stop-band attenuation).
Regarding inductors, it is sometimes possible to find models for them, but mostly you get just an inductance curve (not very helpful), or even just an SRF spec and that's that. Well, SRF at least tells you ballpark how much capacitance you're dealing with -- it's usually a lot more than you'd see on board traces, making the SRF is useful in this case. The SRF can also be due to wave phenomena in the inductor itself (more useful in single layer windings), which is good to know about.
This tolerance is just the variation from one produced capacitor to another right? The real capacitance is usually something like 10% less than the nominal value. So doing cap value * 0.9 as a starting point?
Yes, mfg tolerance, note that's measured at 25C, 0V bias, and freshly soldered so that aging has not reduced the value. Any one of these parameters can push the value outside the tolerance band, so beware. (Typically, temperature doesn't, but temperature does exacerbate saturation under bias; and aging fails tolerance after some years.)
I’m not really sure about this one. I believe if I just take the impedance curve into account I don’t have to deal with an uprating based on frequency correct?
The tick up is just what happens at resonance. You're seeing literally half the picture: as capacitance shoots up towards infinity*, the impedance vector is rotating around to resistive, and then goes inductive.
*Not actually infinity, because Q is finite. It actually peaks, drops through zero and goes negative (with an asymptote of -40dB/dec, because Xc is inversely proportional to F while X_L is proportional; x / (1/x) = x^2 or 40dB/dec so that's how you know what slope it takes). The peak may be too brief to see here, and negative values are weird (indeed, nonsense on a log plot) so they just cut it off before the peak.
So, this is just another manifestation of ESL.
Another thing that left me wondering is people who claim that a capacitor cannot be used above it’s self resonant frequency, because it “looks inductive”. The way I see it if you are filtering a signal and an impedance of 0.01 ohm is good enough, this capacitor would do an equal job to filter a pure sine wave at 700 kHz as it does at 2.5 MHz.
Total bollocks. A capacitor is just fine at high frequencies -- is it a low enough impedance? Fine, you're good, done!
It might not be the most appropriate capacitor. A physically smaller one (say, 0.1uF 0603) will have less ESL and therefore a lower impedance at HF,
completely independent of nominal capacitance value. Same for a wider one (say, 0612 vs 0603), or one with shorter traces and more vias connecting to it.
The capacitance really only factors in to a couple of things:
1. Energy storage, particularly if you're concerned about hold-up time in the application.
2. Bulk capacitance to handle ripple current.
3. Impedance (C + ESR) to suit the control loop compensation.
4. Damping of the rest of the circuit (same idea).
Note that, since #2 usually dominates the others, you may need to deal with the others some other way.
Example: damping of the PDN (power distribution network) can't be done at the bulk-filter end, because of how low the impedance is there. It acts like a short circuit at one end of a transmission line. You must terminate the other end. So, put a lossy capacitor (usually tantalum, but don't ignore ceramic + resistor) there, and you're set.
Now taking the DC bias voltage into account:
So based on this curve if my output voltage is 12V for example, I should multiply the original 22uF by 0.3 to get 6.6uF. And keeping the ESL the same I now get a self resonant frequency of about 2.7 MHz. So for higher dc voltages the capacitor is better at filtering higher frequencies. Does this look right to you?
The numbers are correct, the conclusion is not.
If the total impedance is higher, it's worse at filtering. Impedance depends on the system.
It could well be better
or worse depending on what's attached. Suppose your converter runs at 1.2 or 2.7MHz. Both conditions will be better and worse, respectively!
The easiest way to find out, is to model the system. Put together all you know about parasitics, build a model representative of the layout, and let SPICE do the cranking.
By the way, N identical R+L+C's in parallel, is equivalent to one (R/N + L/N + C*N), so you can use that shortcut to save a lot of mess. Though, you may keep them independent and connect them together with short traces (a few nH) and see what effect that has (typically not much, but worth seeing for yourself).
Interesting things happen when you combine capacitors of different value, especially with notable trace lengths. While one (RLC) is inductive and another capacitive, they have a parallel resonance at the common frequency. The system impedance has two dips (two capacitor SRFs) and one peak (inbetween).
Playing with filter circuits, you will soon realize that you can't just place a dip anywhere you like: you necessarily add another peak, when adding a dip somewhere. Simply connecting capacitors, of random size and value, in parallel, can reduce the minimum impedance, sure -- but it also increases the maximum impedance, and those ratios are related (the Q factor)!
The key is to keep the impedance modest, not to shoot for the least possible. Keep it around ESR, so the network is naturally dampened.
"It" being Zo = sqrt(L/C), for any reasonable pairing of L and C. Pick a peak or valley, and you can eyeball some combination of L's and C's in circuit, which when combined in series and parallel, as appropriate for that resonant mode, yields the given resonant frequency.
HTH,
Tim
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