Cascaded Control Loop System, with different sensor sampling frequencies

[ali80]

Hi
I have a cascaded control loop system (a dc motor running at 1500rpm with speed and current feedback),both sensors (s1=current and s2=speed generate interrupts when their data become available), my problem is that the internal control loop sensor has different sampling frequency than the outer loop sensor(fS1 <> N*fS2),
I'm wondering how and where should I update the inner and outer control loops.
I have thought of several options but non of them feels right to me!
1. Update both loops in a free running timer and update the sensor values in their respective interrupts.
2. Update the inner loop variable(current) in its interrupt and update both inner and outer loops with the same frequency at the outerloop sensor interrupt
3. try resampling so that N*fS1 = fS2

[CM800]

I would imagine that it would be best to update the loops as soon as each piece of data comes in. So whenever the current sensor reads back, update and the same for the other sensor.

[ali80]

I would imagine that it would be best to update the loops as soon as each piece of data comes in. So whenever the current sensor reads back, update and the same for the other sensor.

yeah I forgot to mention this option. I'm annoyed by the variable dead time/latency when using this option, suppose you updated the outer loop, when would the inner loop gets updated, there would be a variable delay between 0 to 1/fS1, though I'm not sure about the consequences.

[IanB]

Your inner loop should be much faster than your outer loop to provide stable control. So exact synchronization between the loop sample rates is not critical. Let's say the inner loop has a scan rate 10x faster than the outer loop. So the outer loop can miss the inner loop update by a maximum of 0.5 in 10 or 5%. It shouldn't make much difference to the overall operation.

[ali80]

Your inner loop should be much faster than your outer loop to provide stable control. So exact synchronization between the loop sample rates is not critical. Let's say the inner loop has a scan rate 10x faster than the outer loop. So the outer loop can miss the inner loop update by a maximum of 0.5 in 10 or 5%. It shouldn't make much difference to the overall operation.

yeah it is about 10 times faster, thanks that's a relief, and I guess the inner loop interrupt should be able to preempt the outerloop interrupt except the sections which updates the reference and feedback variables if I'm not mistaken?

[awallin]

FWIW, if you have access to Matlab with most extras installed (like at a typical University..) then Simulink is the tool to model this. It has 'analog' variables and different sampling methods etc.

[ali80]

FWIW, if you have access to Matlab with most extras installed (like at a typical University..) then Simulink is the tool to model this. It has 'analog' variables and different sampling methods etc.

I indeed have access to Matlab (the project is also a university project), I don't know why it didn't crossed my mind , although I think it is a little tricky to model different sampling rates when fS1 <> N*fS2, thanks anyway.

[MrAl]

Hi,

I am not sure if you are into sampling theory and discrete systems but that would be a good approach.

Also, did you try simulating this with a computer program?  Use your language of choice perhaps.

[ali80]

Hi,

I am not sure if you are into sampling theory and discrete systems but that would be a good approach.

Also, did you try simulating this with a computer program?  Use your language of choice perhaps.

I know a little bit but I always want to learn more,
I usually simulate these kind of circuits in simulink/matlab but haven't simulated this one yet, since fS1 <> N*fS2 you cant just add rate transition block and be done with it.

[MrAl]

Hi,

I am not sure if you are into sampling theory and discrete systems but that would be a good approach.

Also, did you try simulating this with a computer program?  Use your language of choice perhaps.

I know a little bit but I always want to learn more,
I usually simulate these kind of circuits in simulink/matlab but haven't simulated this one yet, since fS1 <> N*fS2 you cant just add rate transition block and be done with it.

Hi,

Well maybe you can use Z transforms.  It's been so long since i did this myself i'd have to look it all up again, but basically from memory the delays can be transformed and then the system can be analyzed using somewhat standard procedures.  A Z transform delay is just z^-n where n is the sampling period delay.  This creates a system similar to that where you would use Laplace Transforms but then you just calculate a little differently.  The results give you some idea what works and what doesnt work because there are ways to tell if it goes unstable, just like in the Laplace domain.