Different die pictures

[T3sl4co1l]

Did you mean https://www.eevblog.com/forum/projects/unknown-circuits-die-pictures/msg5382593/#msg5382593

Tim

[Noopy]

 

Thank you very much! 

[Noopy]

The Intersil ICM7226A is a fully integrated frequency counter that can determine frequencies up to 10MHz. The component with index A is designed to drive 7-segment displays with a common cathode. The ICM7226B, on the other hand, drives 7-segment displays with a common anode.




The test circuit in the datasheet shows how efficiently the ICM7226 is constructed. The module contains an oscillator and directly drives eight 7-segment displays. The outputs, which multiplex the individual digits, are used simultaneously to read in the function selection and the counting range.




The ICM7226 datasheet contains a detailed block diagram showing how the chip does the counting.




The dimensions of the die are 4,3mm x 4,1mm. The image is available in original size: https://www.richis-lab.de/images/counter/01x03XL.jpg (29MB) It can be seen that the design would provide two additional bondpads. However, these bondpads are not metallised, so they can only be used when a different metal layer is used.

The lowside transistors, which control the segments of the active 7-segment display, are located at the top edge. The highside transistors, each of which activates one of the 7-segment displays, are located in the bottom left-hand corner. Repeating structures can be recognised in the core of the ICM7226. The majority of these areas are likely to contain frequency dividers, of which a large number is required.




Test structures are integrated in the top right-hand corner. Next to them are character strings that could be the initials of the developers, among other things.




The revisions of six masks can be seen in the bottom right-hand corner. The designation ICM7226 is shown underneath. Y appears to be the revision of the design. The Y appears several times on the die. If we assume that we are counting backwards from Z, then this is a second revision.

A closer look reveals that a 1 is depicted in a lower position in place of the second 2. This indicates that the design could be used for both the ICM7226 and the ICM7216. All you have to do is change the metal layer.




The ICM7216 offers slightly fewer interfaces due to its smaller housing, in particular the BCD output is missing. Otherwise it is the same module. It therefore makes sense to operate the ICM7216 and the ICM7226 with the same circuit.


https://www.richis-lab.de/counter01.htm

 

[Noopy]

The ST Microelectronics L9101 is a IC that can be found in many vehicle control units built by Magneti Marelli. It appears to have been used only by Magneti Marelli. A datasheet for the L9101 cannot be found. Mouser lists the part, but with the attributes "not available" and "discontinued". The L9101 shown here was retrieved from an ECU.




The circuit around the L9101 in the ECUs shows which functions have been integrated. The module is usually used to read inductive speed sensors, such as those found on the crankshafts of combustion engines. The L9101 is also a transceiver for the K and the L line. These two lines are part of the standardized diagnostic interface via which the status of a vehicle can be read out.

It does not seem particularly obvious to integrate a sensor interface and a bus transceiver in one ASIC. However, there were obviously good reasons to do so. In automotive ECUs, attempts have always been made to integrate circuits and combine them into larger parts. As these are often very specialized functions and circuits, ASICs are created that are often only used in the automotive sector.




The L9101 contains a 2,43mm x 1,85mm die. This image is also available in higher resolution: https://www.richis-lab.de/images/ecu/05x02XL.jpg (19MB)






In addition to the ST logo, the die also shows some character strings. CL001B could be an internal project designation. The letter B could then be a revision. However, this is pure speculation. As described in the context of the NE555 from ST Microelectronics, character strings such as 800C5 appear to describe a process technology or a technology node (https://www.richis-lab.de/555_1.htm). The IC is based on a bipolar process with one metal layer. The numbers 92 could stand for the year 1992.




The reference potential is distributed by a wide frame structure (blue). The L9101 is supplied with +12V (yellow) and +5V (red). Strictly speaking, the +12V potential is the so-called terminal 30, which can also supply slightly higher voltages.




The die clearly shows a division into two parts. Apart from the supply potentials, these two parts have no electrical connection.






Large picture: https://www.richis-lab.de/images/ecu/05x08XL.jpg

The circuit can still be analyzed relatively well. Most of the inputs and outputs have protective diodes, which are not shown here.




The upper circuit, the left part on the die, consists of three blocks.




The two blocks on the left are the receiver circuits for the L and K lines. They have almost the same structure. A differential amplifier receives the signal. In contrast to the rest of the circuit, the differential amplifier is supplied from the 12V potential. This is necessary because the high level of the input signal is 12V. The circuit around Q74 and Q76 ensures that the 12V supply is only active when a 5V potential is also present. This ensures that no current is drawn from the permanently applied 12V potential as long as the ECU is not active.

The reference potential of the differential amplifier is supplied by a voltage divider, which is also supplied from the 12V potential. This makes sense as the high level on the bus fluctuates with this potential. The reference potential is influenced by the output signal of the differential amplifier via a transistor. This results in the hysteresis required for evaluating the bus signals. This is followed by a simple output stage. In addition the inverted level of the K line is routed to the third circuit block.




The right-hand block is the transmitter for the K line. Here, too, there is a differential amplifier at the input. The reference level is obtained from the 5V potential. The open collector output of transistor Q53 on the far right is ultimately controlled. If a high level is present at the input, the output becomes inactive. Transistor Q50 ensures that this happens directly and without delay.

The output of a low level is much more complex. If the input changes to a low level, the differential amplifier at transistor Q46 also outputs a low level. This causes all the transistors connected there to switch off. As a result, transistors Q51, Q50 and Q55 are inactive in the output area. The current through R59 activates the driver Q54 and thus the output transistor Q53.

The low level represents the dominant state on the K line. A malfunction of an ECU could therefore easily block the entire bus by outputting a permanent low level. For this reason, the L9101 only allows short low pulses. If the output is switched active, the capacitor C5 is simultaneously charged via the current source Q61. The voltage divider R63/R64 determines the maximum voltage. As soon as the capacitor voltage approaches this voltage, current flows trough transistor Q60. At the same time, the current from current source Q63 flows through transistor Q58. This in turn activates transistor Q55, which finally deactivates driver Q54 and thus also the output transistor.

The signal from the receiver circuit of the K line controls the transistor Q62. This link ensures that the transmitter remains deactivated if a low level is already present on the bus. Transistor Q56 represents a further path that can deactivate the output. This transistor is controlled via a chain of five Z diodes that are connected to the 12V potential. As these are emitter-base paths, it can be assumed that the breakdown voltage is in the range of 5-6V. This means that the output is deactivated as soon as the 12V potential rises above 25-30V.




The second part of the L9101 enables the evaluation of an inductive speed sensor.




One challenge when evaluating an inductive speed sensor is that the level changes significantly with the speed. The datasheet for the Bosch IS-C speed sensor clearly shows this relationship. As the signal is generated by induction, it is also not a clean square-wave signal, but rather sharp pulses. The environment often adds considerable interferences, which further complicates the evaluation. Nevertheless, the speed must also be detected in transient states of the motor. In addition, the gear to be evaluated usually has a larger gap at one point. This difference must be evaluated in order to determine the current angle of the motor.




Pins 6 and 7 are the inputs for the speed sensor. They lead to two symmetrical paths that are reminiscent of a differential amplifier. However, the two lines are merely a signal adjustment. The circuit section around the transistors Q38-Q40 limits the level of the input signal.

The circuit around the transistors Q36/Q37 and the circuit around the transistors Q43/Q44 control the transistor pairs at the upper and lower ends of the two strings and ensure a certain quiescent current. This type of quiescent current generation seems unusual. It probably has special advantages here.

The modified signal from the speed sensor is finally passed on to the next stage of signal processing via transistors Q32/Q33.




After signal matching, the signal passes through a voltage amplifier stage whose output is the transistors Q20/Q21. The circuit section around Q22 appears to be a current limiter. This is followed by the output stage, which outputs the processed signal at pin 10.

The potential at transistor Q24 also controls the current source Q15 by diverting its supply via Q13. The current output by Q15 is fed back to the input, where it provides positive feedback. This results in the desired comparator effect.




In addition to the current source Q15, the circuit on the far right represents another positive feedback. Here, transistor Q8 feeds the current into the input. The amount of current is defined by the current sink Q5. A large voltage divider supplies the potential that controls the current sink. A resistor with an earth reference must be connected to pin 8. The size of the resistor determines how much current flows through the transistor Q5.

Transistors Q1 and Q2 determine whether the current of the current sink is mirrored to the input or not. They can accept the current and thus divert it. Q1 is controlled by the output potential at pin 10. Q2 can be activated by the evaluating microcontroller via pin 9.

The L9101 thus offers the option of setting the hysteresis of the comparator via an external resistor and also switching it via a microcontroller. As already described, the evaluation of an inductive speed sensor is challenging. The variability is a great advantage here.




The module shown here on the left is clearly labeled differently, but contains the same design. There are no recognizable differences. The L9101 on the right was purchased new from China. It is very pleasing that this is apparently an original part.


https://www.richis-lab.de/ECU05.htm

 

[D Straney]

Love the full die-shot-to-schematic transistor-level breakdown of how it works!  Some parts of the circuit make me wonder why they did it that way, like the transmitter's max-pulse-width timer: seems like it would be easier to stick something (like R51 & Q55's base) directly in the collector path of Q60, rather than doing the weird thing with Q58 and Q59 that I don't understand.  (Not sure if it's relying on the base current draw from Q60 to shift the voltage divider's level?  It almost looks like Q60 is just setting up a Vbe-offset on the threshold voltage so that Q58 & Q59 can do a Vbe-free comparator action, if Q60 had constant bias current)

I'm assuming with the tiny on-chip capacitances available that the capacitor-charging current is much smaller than the current required by Q55's base to make an impact on the output drivers, but doesn't seem like anything that a 3-transistor double-Darlington can't fix   I'm sure there's probably a good reason for the way it was done though; just my back-seat-driver opinion.

[T3sl4co1l]

I don't quite understand the timing and logic here, but I'm also not familiar with the bus and operation so I assume it just works out for all of that.

I think what they're doing is, Q61 charge current, Q60 voltage clamp (a Vbe above time-out threshold), Q58-Q59 is the timer diff pair / comparator, and Q55 is wired-NOR with Q51 (but not also Q50 so no fast turn-off; without hysteresis, it's not going to be terribly sharp anyway).  So Q52/Q62 are active often, V(C5) remains low and pin 4 gets buffered to pin 3; if pins 2 and 4 remain high for enough time, the output is forced off.

I wonder why R63 or R64 isn't a stack of diodes, or a zener.  R64 zener would give more stable timing (independent of +V); R63 a few diodes would give maximum range (minimum C5 area).  Perhaps they needed to limit Veb; but, those are lateral PNP and ~30V should be the limit.  Perhaps also something about Early effect, I *think* lateral are rather poor in that respect, and maybe they didn't want to run all the way to the rail, nor spend the area on cascodes.

(This is just ye olde single-bipolar (NPN + lateral PNP) process, right?)

Tim

[Noopy]

I´m sure there is some magic we will never understand (without a hint). 

And sometimes the engineers don´t integrate the best solution because they are in a hurry or they simply don´t belong to the master class. 

This is just ye olde single-bipolar (NPN + lateral PNP) process, right?

Exactly! 

[magic]

Looks like lots of fun

The right-hand block is the transmitter for the K line. Here, too, there is a differential amplifier at the input with a reference level obtained from the 12V potential. The open collector output of transistor Q53 on the far right is ultimately controlled.

Actually, according to your schematic, the whole K transmit block is powered from the 5V rail, which makes a lot of sense because its input is probably coming from a 5V MCU and the logic threshold should be related to that.

I think what they're doing is, Q61 charge current, Q60 voltage clamp (a Vbe above time-out threshold), Q58-Q59 is the timer diff pair / comparator, and Q55 is wired-NOR with Q51 (but not also Q50 so no fast turn-off; without hysteresis, it's not going to be terribly sharp anyway).

That's how it seems. Not sure what's the point of Q60, though, and if very high precision isn't required then a diff-pair is overkill too.

I wonder why R63 or R64 isn't a stack of diodes, or a zener.  R64 zener would give more stable timing (independent of +V); R63 a few diodes would give maximum range (minimum C5 area).

This runs off the (reasonably regulated, I presume) 5V rail so there shouldn't be much supply variation. And whatever there is, is compensated by Q61 current being proportional to supply voltage - these current sources here are biased by a voltage divider (R52, R53).

[T3sl4co1l]

Yeah, I've used a circuit before where essentially Q60 Ic is used for the output. Beats me!

Diff pair inputs seem overkill as well; surprised not just TTL style.

Tim

[Noopy]

Looks like lots of fun

Absolutely! 

The right-hand block is the transmitter for the K line. Here, too, there is a differential amplifier at the input with a reference level obtained from the 12V potential. The open collector output of transistor Q53 on the far right is ultimately controlled.

Actually, according to your schematic, the whole K transmit block is powered from the 5V rail, which makes a lot of sense because its input is probably coming from a 5V MCU and the logic threshold should be related to that.

Yes, that was a mistake. The transmitter is supplied from the 5V potential.
Just the 12V overvoltage circuit has a connection to the trasmitter.
Thanks for the hint!

[Noopy]

The American company Rainbow Technologies was founded in 1984 and developed products for encrypting data. Rainbow Technologies later merged into various other companies. The advertisement above is taken from the Network World magazine from April 5, 1999 and shows the so-called i-Key, a USB stick that can be used to log on to a server in a more secure way. The PCI accelerator cards NetSwift and CryptoSwift are also advertised. These cards can be used in servers to perform the necessary cryptographic calculations and thus reduce the load on processors.




The above TQFP-208 IC with the designation 105244-002 is used on the accelerator cards described above.






The package contains a very large die with an edge length of 11,1 mm. The die has 456 contact pads, of which exactly 208 have been contacted. There is an additional pad in each corner, presumably for testing purposes.

A much better picture of the die follows. Interestingly, the lower picture shows the partitioning of the surface most clearly. The upper area appears to contain mainly logic circuits. In the lower area you can see several evenly structured areas, which probably represent different memory volumes.




The surface of the die is coated with a polyimide that fortunately can be burned quite good.




This image is available in a higher resolution and shows much more details:
https://www.richis-lab.de/images/crypt/01x05XL.jpg (43MB)
Surprisingly, however, it is less helpful as an overview image than the image above with its significantly poorer quality.




The chip was obviously manufactured by IBM.




The character strings in the top right-hand corner were structured with different masks and reveal some details about the process. The character strings 3734A could stand for the design. The characters in front of it are more interesting: MT, V3, M3, V2, M2, V1, M1, CA. Obviously MT is the "metal top", i.e. the uppermost metal layer. V3 are the vias to the next metal layer M3. This is followed by the vias V2 to the metal layer M2 and the vias V1 to the metal layer M1. CA should then be the contacts to the active area.




There are four more mask designations in the top left-hand corner, but these are not easy to assign: MC, PC, RX, RW (?).




The masks used are shown once again in the upper edge.




The four metal layers conceal the active structures. Even the lowest metal layer can only be seen in a few places.




In the few open areas, one can at least recognize the polysilicon layer (pink).




In the metal layers, the smallest structures are already smaller than 1µm.


https://www.richis-lab.de/crypt01.htm

 

[Noopy]

The TSA5510 is a circuit developed by Philips that was used in the receivers of analogue televisions. The TSA5510 is described as a "1.3 GHz I²C bus controlled frequency synthesiser". In fact, the component itself does not generate any frequencies, but only realises a PLL control around the receiver and its oscillator.

The picture above, which is shown in the TSA5510 datasheet, shows the typical circuitry. The clock signal generated by the oscillator in the receiver is read in via pin 15. The TSA5510 compares this clock signal with a reference clock. Deviations are readjusted using a transistor on pin 18. Control takes place via an I²C bus. In addition, the TSA5510 offers eight inputs and outputs with different functionalities. As can be seen in the block diagram, this can be used to realise band switching, among other things. In addition to the TSA5510, the TSA5510T was also offered. The variant with the index T has only five of the inputs/outputs just described and could therefore be integrated into the smaller DIL-16 package.




The datasheet also contains a block diagram of the TSA5510. The signal of the oscillator to be controlled arrives in the top left-hand corner. The clock signal is first divided by 8 and then further divided by a programmable factor. Finally, a comparison is made with a 4 MHz oscillator whose frequency is first divided down to 7,8125 kHz. Depending on the result of the comparison, the output on pin 18 is activated.




The two components above came from an internal Philips collection. In addition to the designation, the housing is labelled with the character sequence C2B. This could be a revision of the design.






The dimensions of the die are 2,8mm x 2,0mm. The design has two metal layers. The surface appears blotchy, which makes it more difficult to analyse the circuit in detail. This image is also available in higher resolution: https://www.richis-lab.de/images/gen/04x05XL.jpg (28MB)




R2452 could be an internal designation of the design. C could then stand for a revision.





This TSA5510 also comes from the internal Philips collection. In contrast to the first two components, the metal cover was only fixed with an adhesive strip. Instead of C2B, this module is labelled C2.




The die of this TSA5510 is very similar to the first two TSA5510s, but there are also some differences in the details. The two metal layers are clearly visible here. The surface is much cleaner. This picture is also available in higher resolution: https://www.richis-lab.de/images/gen/05x02XL.jpg (24MB)




An R and the logo of the I²C bus are shown on the left edge. A leading 0 has been added to the presumed internal project designation. In addition, C2 is now at the end. Contrary to the designation on the housing, this suggests that this module is an update of the first variant. This is also supported by the now added copyright symbol.


https://www.richis-lab.de/gen04.htm

 

[Noopy]

The ATtiny10 is a microcontroller in a very small SOT-23 package. Alternatively, it is also available in a UDFN housing. Supplied with 5V, the ATtiny10 operates at up to 12MHz. It has 1kB Flash and 32B SRAM. At 12MHz the current consumption is 3,7mA. At 1,8V and 1MHz, 200µA are sufficient to operate the microcontroller.




The ATtiny10 offers four outputs, a 16-bit counter, two PWM channels, a comparator and an 8-bit ADC that can operate four channels.




In addition to the ATtiny10, the datasheet also lists the ATtiny5 with only half as much flash memory and the variants ATtiny9 and ATtiny4, which lack the ADC. It is quite possible that all four microcontrollers use the same die and only certain areas are deactivated.




The dimensions of the die are 1,38mm x 0,93mm. The flash memory is located in the top left-hand corner. The memory itself is covered by the top metal layer. With its surrounding circuitry, the memory takes up a large part of the surface. The strip in the top right-hand corner could be the SRAM. Analogue circuit parts are integrated at the right edge. This image is also available in higher resolution: https://www.richis-lab.de/images/uC/04x04XL.jpg (18MB)




The design was obviously created in 2008.




AT 35470 is probably the internal project designation.




Several masks are depicted on the lower edge. Three layers of metal appear to have been used. The letter at the end of each mask is probably the revision. This would correspond with the revisions listed in the datasheet. Revision E was recorded there in February 2010.


https://www.richis-lab.de/uC03.htm

 

[magic]

The TSA5510 is a circuit developed by Philips that was used in the receivers of analogue televisions. The TSA5510 is described as a "1.3 GHz I²C bus controlled frequency synthesiser". In fact, the component itself does not generate any frequencies, but only realises a PLL control around the receiver and its oscillator.

Although it doesn't produce the RF output itself, it has to handle 1.3GHz on pins 15, 16 so it's a fairly fast analog (mixed signal, really) chip. It appears to be made on a high speed noncomplementary bipolar process, denser than typical jellybeans (usually a lateral PNP is about the size of a bond pad, here much smaller) and probably limited to low voltage.

The RF input goes to an NPN differential pair amplifier and then apparently a three stage counter implemented with NPN differential pairs and emitter followers. This was presumably the only way they were able to handle such frequencies on this process. The rest looks like boring I2L logic working at somewhat lower frequencies, although I'm not entirely sure where the injectors are. The smaller than usual feature size makes things difficult to see.

Digital IOs are similar to TDA8445 - lateral PNP comparators feeding NPN flip-flops for the input, open collector NPNs for the output.

[Noopy]

The TSA5510 is a circuit developed by Philips that was used in the receivers of analogue televisions. The TSA5510 is described as a "1.3 GHz I²C bus controlled frequency synthesiser". In fact, the component itself does not generate any frequencies, but only realises a PLL control around the receiver and its oscillator.

Although it doesn't produce the RF output itself, it has to handle 1.3GHz on pins 15, 16 so it's a fairly fast analog (mixed signal, really) chip.

Indeed nevertheless it´s not an easy job the TSA5510 has to do. 


Thanks for your interpretation. As you said it´s a alittle hard to read.

[Noopy]

The Atmel ATtiny841 operates at a supply voltage of 5V with up to 16MHz. The microcontroller contains 8kB flash memory, 512B EEPROM and 512B SRAM. A variant with 4kB flash memory is marketed under the designation ATtiny441.




The ATtiny841 offers 12 IOs. It has one 8-bit and two 16-bit counters. Analogue signals can be processed with two comparators and a 10-bit ADC.




The edge length of the die in the ATtiny841 is 2,0mm. This image is also available in higher resolution: https://www.richis-lab.de/images/uC/04x04XL.jpg (16MB)




The design obviously dates back to 2012. AT 354A5 is most likely an internal project designation. Ten masks are shown on the right-hand side. The revisions extend up to the letter C, which matches the revisions described in the datasheet. Compared to the ATtiny10, mask 20 was added. Perhaps it was needed to integrate the EEPROM.


https://www.richis-lab.de/uC04.htm

 

[Noopy]

Update ATtiny10:




We talked about the ATtiny9, ATtiny5 and ATtiny4 and that all three probably use the same design.
Now i have found the ATtiny4 at Zeptobars: https://zeptobars.com/en/read/atmel-tiny4-attiny4-microcontroller
It is the same as far as we can say from the pictures.




After four hours in a glass etching paste, the hydrofluoric acid released has dissolved any silicon oxide. Metals, polysilicon and the substrate are only slightly affected. However, over the long exposure time, the silicon oxide layers under the following layers also dissolve in addition to the top passivation layer. As a result, all the layers peel off and the substrate can ultimately be viewed uninterrupted. The structuring of the active areas has left height differences on the substrate, which often make it easier to identify the integrated functional blocks.

High resolution: https://www.richis-lab.de/images/uC/04x08XL.jpg (21MB)




The structure of the flash memory is much clearer without the metal layer. The memory cells themselves are the densest structures on the die. The repeating elements of the row and column selection can be seen on the left and above the surface. The larger structures on the right are probably auxiliary circuits. Underneath, for example, there could be a charge pump, which is usually needed to write to Flash or EEPROM cells.




The datasheet specifies the memory architecture as 16x512. To the left of the memory you can see 16 larger, identically constructed circuits (red). This is most probably where signal processing takes place to read or write to the memory. On the left edge of the memory, 4x16 identical rectangles can be recognised (yellow). On closer inspection, the rectangles are divided into two parts. Only 16x4 lines can be recognised in the top metal layer (left image). However, further horizontal lines can be seen underneath. Within the storage area there are 2x8 blocks with 8 elements each. It can therefore be assumed that the memory has 128 lines. At the top edge there are 2x35 rectangles, which indicates 70 columns. For the usable 1024B, 64 columns would be sufficient. Dummy structures (cyan) are located at all edges of the memory. The additional 6 columns, totalling 96B, are therefore functional memory cells.






A look at the datasheet shows how at least some of the additional memory cells can be explained. The I/O Space and SRAM areas are located elsewhere. However, the memory cells below them are all located within the one Flash memory. In addition to the lock bits, the Flash memory also contains the configuration bits, the calibration bits and the device ID. Although these functions only require a few memory cells, they occupy relatively large areas. This presumably facilitates a certain functional separation.

The placement of the lock bits within the large Flash memory is advertised as particularly secure. If the lock bits are located elsewhere in the die, you can try to selectively erase them with UV light and then read out the memory. Within the program memory, it is much more difficult to influence the lock bits without deleting the programme itself. This is especially true if the memory cells are covered by a metal layer. If it is not possible for you to cut a window into the metal layer, the necessary amount of light must be directed into the relevant memory cells via reflections. In the direct vicinity of the program memory, this is even less of an option.




Without the metal layer, you can now see the structure of the SRAM more clearly.




The logic area appears chaotic. Depending on the desired function, doped areas were created here that in combination with the polysilicon layer on top generate transistors as necessary.




Various structures are located on the right-hand side of the die. Integrated into these are analogue circuit parts and functions such as the counter. In this context, a large and surprisingly uniform structure reminiscent of a memory appears unusual. However, the irregular contacts in the centre of the area are atypical for a memory.

After removing the metal and polysilicon layers, a uniform structure with deviations can also be seen underneath. A closer look reveals that there are 8 rows, with 64 lines leading into the structures from above and below.




It can be assumed that these are the registers that configure functions such as ADC, comparator, counter... The register block has 64x8 memory cells, which matches the visual appearance of the block above. It makes perfect sense to place the configuration registers in the area where the functions to be configured are located. The partially exclusive contacting within the registers probably ensures that certain blocks can be read or written to directly and therefore very quickly.


https://www.richis-lab.de/uC03.htm

 

[T3sl4co1l]

Interestingly, reserved bits, in 100% of my experience, are always absent.  So the grid is interesting. Perhaps they can stuff a little logic into the gaps?  Alternately, with so little SRAM as such, it's maybe a surprise they don't just let it float around as registers and gates in the logic fabric, heh.

Mind, that's far from comprehensive, even across all registers of one given device, let alone all devices -- I've only done spot checks here or there, but, I have yet to find anything suspicious.

Tim

[Noopy]

Interestingly, reserved bits, in 100% of my experience, are always absent.  So the grid is interesting. Perhaps they can stuff a little logic into the gaps?  Alternately, with so little SRAM as such, it's maybe a surprise they don't just let it float around as registers and gates in the logic fabric, heh.

Perhaps the reserved bits are absent but just because they can not be adressed.
But it´s also possible that Atmel used unused register areas to insert some logic. That would explain why the structure in the metal layer is "a little chaotic".