Hi microbug and the group,
I was a little late to the party. I didn't realize that you were discussing my project till today.
I can answer a few of the questions that have been raised, some of them have already been answered correctly, but you might as well hear if from me.
1) Two supplies, positive and negative voltages were used to make the circuit design easier. By having two supplies I am not restricted to rail-to-rail op-amps. Strictly speaking you don't rail-to rail performance, but you need an op-amp that includes the negative rail in its common mode range. The output does not need to go the negative rail because of the gate threshold voltage in the MOSFET. The LM324 will work. The LT1014 is a better LM324.
2) The inverting configuration allows me to sum two signals. There is a dc level, one potentiometer and a pulsed level the other potentiometer. This let you set a minimum level and maximum level for transient load testing.
The load is connected to a power supply and the pulsating load current can be used to evaluate the transient performance of the power supply.
3) 500Hz was chosen as the test frequency. Most power supplies being tested will settle (recover) within 1ms. The oscillator is part of the real circuit. If I needed a pulse generator for the modelling I would have just used a voltage source and the PULSE directive.
The load was not designed for a specific job. It was designed to test generic power supplies. I have built several versions. The original was 5A dc + 5A pulsed. I then built a low current version that was 1A dc plus 1A pulsed.
4) The capacitor in the op-amp circuit is to ensure control loop stability. This was discussed at length in my original thread.
It is important that the load is faster than power supply being tested. This was illustrated in this message:
https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/msg1128310/#msg11283105) The circuits presented with the IXYS MOSFET, was theoretical. I have not built and tested this version. It was done at the request of forum member BravoV. It should work because it is designed using the same principles as the loads that have been built and tested.
6) Kerry Wong's design
http://www.kerrywong.com/blog/wp-content/uploads/2017/01/eloadcircuit.pngThis circuit relies on the relative low bandwidth of the LT1636 to get loop stability. The LT1636 has a GBW product of 220kHz. The circuit also lacks an RC network across the input.
The need for the RC network is discussed in my Dynamic load thread. The network can be seen in Dave's latest video of the Rigol load:
![](https://www.eevblog.com/forum/projects/can-someone-explain-this-dc-load-circuit/?action=dlattach;attach=352074;image)
7) Cload op-amps
A lot of people think that you need to use an op-amp that has been designed to drive capacitive loads. This is not the case, so long as the op-amp is separated from the capacitive load by a low value resistor. If you look at the gate currents in the model, you will find that they are quite low.
The single rail load circuit:![](https://www.eevblog.com/forum/projects/can-someone-explain-this-dc-load-circuit/?action=dlattach;attach=352076;image)
Modeling results:
![](https://www.eevblog.com/forum/projects/can-someone-explain-this-dc-load-circuit/?action=dlattach;attach=352078;image)
I have attached the LTspice model for those playing along at home.
Regards,
Jay_Diddy_B