... There will be 24 of these in total...
...Each channel must be able to handle 4A, at 48V (24V will be more common in practice)
That's significant power being turned on and off, you will need to consider parasitic inductances of a practical wiring system.
Some clamping may be needed on the FET, and to manage RFI you may need to carefully slow the gate drive slew rate, and trade off some loss for lower RFI.
An increased gate resistor is sometimes enough.
As already mentioned, 3v3 is a bit feeble for MOSFET power drive, and with that many amps & channels, you need a gate driver with some ground bounce difference tolerance.
eg a newer gate driver like UCC44273 (etc) Single-Channel Low-Side Driver has added features like
• 5-V UVLO
• Ability to handle negative voltages (–5 V) at inputs
• Fast propagation delays (13 ns typical)
• Fast rise and fall times (9 ns and 7 ns typical)
• 4.5-V to 18-V single supply range
• Outputs held low during VDD UVLO (ensures glitch-free operation at power up and power down)
• TTL and CMOS compatible input-logic threshold (independent of supply voltage)
• Hysteretic-logic thresholds for high-noise immunity
You might even consider opto isolation, to keep the noisy power signals completely away from your MCU.