Cable tester/TDR strange result

[jmw]

I made a signal generator based on W2AEW's 74-series oscillator design. When I tested it with a length of 50 ohm coax, the results were as expected. The voltage just about doubles on the second step up, so the generator is a good match to the cable.



When I terminated the cable with a short, the voltage levels change. If the signal initially sees an load impedance of 50 ohm from the coax, the voltage across a 50 ohm load should be about 1.65 V, and it can't "know" about the short until the wave reflects back, why is the initial voltage now around 2.2 V?

[dmendesf]

Show us the circuit... But if the initial condition is different it's probably because a DC current is passing thru the 50 ohms.

[jmw]

Sure. This is what I used for simulation. The inverter is 74LVC14A. R6 is the cable load, and R7 + C4 are the oscilloscope input impedance.

[tggzzz]

Sure. This is what I used for simulation. The inverter is 74LVC14A. R6 is the cable load, and R7 + C4 are the oscilloscope input impedance.

(Attachment Link)

Oh come on, give us all the information: what's

• Rs?
• the output impedance or invert14a?
• decoupling capacitors?
• physical layout

The latter two are critical.

Please say you didn't use a solderless breadboard; if you did, you'll need to include parasitics in your simulation.

[magic]

For the record, here's the setup you should be using:
generator - short cable - BNC tee on the scope - long cable - optional termination

Also, the period between pulses should be at least two propagation delays long, for the whole length of cable to settle at 0V before another pulse.

If you can get these two waveform from the above setup by simply switching on/off a short across the free end of the cable, I would guess that you must have been visited by aliens

[jmw]

Alright, Rs is there in the simulation file (180 ohms). Based on figures in the TI datasheet, the output impedance of the SN74LVC14A is 23 - 29 ohms. Let's call it 25 ohms. So (25 + 180)/4 = 51.25 ohms output impedance for 4 drivers in parallel.

Let's look at the physical layout. The component numbers are different than the simulation file. 2-layer board, bottom layer is a ground pour with one signal trace around U2 to route the first-stage output to the input of the four second-stage drivers. Output traces on the 4 drivers were length-matched to 7 mm, though probably unneeded given the 1 ns(-ish) rise time of the 74LVC.

U1 = 3.3 V / 150 mA-rated LDO
C1 = 100n 0603
C2 = 1u 0805
C3 = 100n 0603
U2 = SN74LVC14A VQFN-14
R1 = 6.8k 0603
C4 = 47n 0603
R2 = 180 0402x4 network

DC power is from a barrel jack, signal out is through a BNC end-launch connector. The BNC output is coupled to a T-connector that goes into the oscilloscope, and the other end going off to the cable.

[tggzzz]

Alright, Rs is there in the simulation file (180 ohms). Based on figures in the TI datasheet, the output impedance of the SN74LVC14A is 23 - 29 ohms. Let's call it 25 ohms. So (25 + 180)/4 = 51.25 ohms output impedance for 4 drivers in parallel.

Let's look at the physical layout. The component numbers are different than the simulation file. 2-layer board, bottom layer is a ground pour with one signal trace around U2 to route the first-stage output to the input of the four second-stage drivers. Output traces on the 4 drivers were length-matched to 7 mm, though probably unneeded given the 1 ns(-ish) rise time of the 74LVC.

You may be interested in https://www.eevblog.com/forum/testgear/show-us-your-square-wave/msg1902941/#msg1902941 Note <300ps risetime, and the resistor value.

[magic]

Okay, so I gather that frequency of that square wave is rather low, just a few kHz apparently? That's good.

The truth is that there is simply no way that what you see really happens

The generator has nothing to do with it. Its output voltage and impedance is what it is and the cable's impedance is what it is too and these alone determine the height of the initial step.

So if you really see a different step, one of those must have changed. Maybe some connector somewhere is lousy, maybe you used a different cable for the measurements, maybe the regulator goes bonkers under 66mA output current, you get the point. Probe around and see what's going on.

What's the length of all the cables involved?

[RoGeorge]

When I terminated the cable with a short, the voltage levels change. If the signal initially sees an load impedance of 50 ohm from the coax, the voltage across a 50 ohm load should be about 1.65 V, and it can't "know" about the short until the wave reflects back, why is the initial voltage now around 2.2 V?

Ideally, for the period of time between the rising edge and the return of the reflection, the waveforms should be identical, no matter the other end is shorted or opened, and I bet this is how it really is, but only at the very first rising edge.

For the following consecutive edges, a DC component starts to build up, so after many oscillations, a DC current will appear, too.  This DC current is different in the two situations (short vs open), and the IC's gates act different under a bigger DC load.

[magic]

Not really. An open or shorted line driven to ground through proper termination will settle down to idle state (no voltage, no current anywhere) within one round trip time. If termination is mismatched, it will slowly settle over a few RTTs.

Proof by SPICE below

[RoGeorge]

The simulation is unrelated with what I was talking.

[StillTrying]

Does the time delay accurately give the cables length, I make it 4.4 m.
Could the cable's dielectric be that bad with a ~2V change in voltages, somehow.
It must be the 74LVC14's 3.3V changing between the open circuit and short circuit tests.

[jmw]

I think I found the culprit: it's bad power! I probed the LDO regulator output and it's trash; not flat at all. I bodged a connection from the 3V3 net to a lab power supply and the voltage levels are the same for both open and short. Now I need a find a better LDO that doesn't tap out at 50 mA...

[tggzzz]

Do you have any comments on figures 14 and 15 in the NCP551 data sheet?

[jmw]

I can see now why there's a problem from those charts. The average current draw from the shorted configuration was 50 mA, and the duty cycle is close to 50% so it's switching about 100 mA.

I haven't done a wide survey of LDO parts. That was a part family I've used before, so I will look for parts with faster load regulation and also ones with a higher max current so I'm derating it sufficiently. Any recommendations off hand?

[magic]

capacitors

edit

And by the way, I agree with tggzzz that your output resistors are suspiciously low. My measurements of SN74LVC2G14 indicated 8~9Ω of output resistance per pin while driving 200Ω load, tggzzz says 7Ω for 300Ω load. The exact value may vary with output current (FETs aren't exactly resistors) so do your own testing. Simply connect 50Ω load, override the circuit to output 3.3V permanently and measure the exact output voltage with a DMM.

A slight mismatch may be the reason why the falling edge doesn't fall all the way to zero right away. You will probably find that the output voltage into proper termination also isn't exactly 50%.

The initial overshoot and ringing could be improved by bringing the 100nF capacitor closer to the IC, but it seems you are already close to the limits of your chosen package here.

[jmw]

The datasheet (https://www.ti.com/lit/ds/symlink/sn74lvc14a.pdf) lists V_OH = 2.3 V (min) at VCC = 3 V and I = 24 mA, and V_OL = 0.55 V (max) at same VCC and current levels, so that where I came up with (3 V - 2.3 V)/(24 mA) = 29.2 ohm and (0.55 V)/(24 mA) = 22.9 ohm. 4 x 180 ohm seems to be a good match, as in using a 50 ohm termination on the cable you have to look closely to discern a second jump. It's still probably tunable for that last 1-2%.

Switching to 0402 for 100 nF to get it ever so closer to the IC is doable, as is going to 4 layers. I'll have to test out bodging bulk capacitance onto the board. OTOH, there's still the question if there's a categorically better LDO to use than NCP551.

[tggzzz]

The V_OH I_OH type calculation is principally useful at "DC", i.e. when the transition has completed. Where purity of the transition is more important, the output resistance at other points is more important, and will be lower. The difference between the two will be minimised by using more gates, since each transistor will not have to be supplying the full current.

Hence the best output resistance, which will have to be determined empirically, may depend on whether you are interested in a "short range" or "long range" TDR.

Having fewer gates in a package shares the effects of package lead resistance/inductance across packages, and allows more capacitance to be placed near each gate. Those are good w.r.t. the edges, as is having a solid ground plane and power plane as close together as possible.

[magic]

The datasheet (https://www.ti.com/lit/ds/symlink/sn74lvc14a.pdf) lists V_OH = 2.3 V (min) at VCC = 3 V and I = 24 mA, and V_OL = 0.55 V (max) at same VCC and current levels, so that where I came up with (3 V - 2.3 V)/(24 mA) = 29.2 ohm and (0.55 V)/(24 mA) = 22.9 ohm. 4 x 180 ohm seems to be a good match, as in using a 50 ohm termination on the cable you have to look closely to discern a second jump. It's still probably tunable for that last 1-2%.

You are right in principle, but this is the worst case output resistance guaranteed over the entire -40~125°C temperature range at VCC=3.0V. It's going to be lower in practice, lower still if the device doesn't operate at temperature extremes and slightly lower at VCC=3.3V too.

Sorry, no idea about fast LDOs.