Boost Converter PCB Layout

[Electr0nicus]

Hi

I currently designing a battery operated device. It runs from a 1s3p Li-ION 18650 battery pack. To generate the 12V System rail, I use a LTC3786 Boost Converter. I spent the last few days with shuffling around the components and finding an optimal layout. So I came up with the following layout, which in my opinion, is very good. But still I'm not 100% confident if it is really as good as I think. So maybe one of you more experienced guys can have a look and suggest things which can be made better.





Kind regards
Gregor

[sacherjj]

You have a very copper heavy layer (which is good).  There are components that most likely need better thermal isolation.  An example of this is CP2.  Good thermal isolation on one pad, and none on the other.  Same with CP1.  Rsense has no thermal isolation, which may or may not be fine.

None of these would be a problem with hand assembly, however I would not be surprised to see a large number of CP1 and CP2 tombstone with reflow.  The thermal isolated pads will cool down faster than full copper pads.  This can make the cooling solder lift the component out of the still molten full copper pad.

[AndyC_772]

The voltage developed across RSNS is going to be small, and any noise picked up on top of it will affect the stability of your regulator. Is it not possible to flip the overall layout so that RSNS is next to the controller?

[nctnico]

I didn't read the datasheet but there is a voltage feedback loop so I think Rsense is there to limit the current through the MOSFET.

Then again I would try to put CP1, L1 and BMOS together as close as possible. A lot of current is circulating in those parts.

[Electr0nicus]

You have a very copper heavy layer (which is good).  There are components that most likely need better thermal isolation.  An example of this is CP2.  Good thermal isolation on one pad, and none on the other.  Same with CP1.  Rsense has no thermal isolation, which may or may not be fine.

None of these would be a problem with hand assembly, however I would not be surprised to see a large number of CP1 and CP2 tombstone with reflow.  The thermal isolated pads will cool down faster than full copper pads.  This can make the cooling solder lift the component out of the still molten full copper pad.

That will be indeed a problem with reflow soldering. But how will thermals affect the high current properties of the components, as you literally reduce the "trace" width on every component pin? Will it be tolerable if all pads have no thermal isolations, as they will approximately cool down equally fast?
Although this problem doesn't bite me yet, because I don't have the intention to produce more than 10 PCBs any time soon

The voltage developed across RSNS is going to be small, and any noise picked up on top of it will affect the stability of your regulator. Is it not possible to flip the overall layout so that RSNS is next to the controller?

Yes I've tried that. It shortens the RSNS leads but makes many other things worse. As your Mosfet gate drive signals getting longer and will be routed under the inductor and switching node, also the feedback trace will have to be routed directly on the bottom layer from  VOUT to the regulator on top. And that feedback trace I consider much more sensitive than the RSNS traces. In my current layout it's very short and on the "quiet" part of the PCB.  Also the chip will be much nearer to the inductor. The sense lines themselves are low impedant and the loop area is very small, so interference should be minimized. The highest di/dt occours around the TMOS, BMOS and the output caps. The input caps have a relatively low di/dt.

I didn't read the datasheet but there is a voltage feedback loop so I think Rsense is there to limit the current through the MOSFET.

Then again I would try to put CP1, L1 and BMOS together as close as possible. A lot of current is circulating in those parts.

I agree with your first statement, but disagree with your second one. It is a boost regulator. So the currents trough CP1 and L are really slow rising, as the inductor slowly charges up, the current rises. The really high currents flow when the inductor is switched off and the energy has to be transfered to the output caps. In the datasheet they write:

Put the bottom N-channel MOSFET MBOT and the top
N-channel MOSFET MTOP in one compact area with
COUT .

http://cds.linear.com/docs/en/datasheet/3786fa.pdf

[megajocke]

I would rather want the output capacitors as close as possible to the MOSFETs because this is a boost converter. This is the loop with the largest di/dt, and keeping its inductance low helps combat EMI and keeps efficiency high.

[Phaedrus]

RSNS needs to be as close to the controller as physically possible or you're going to get noise on your output. It also needs thermal isolation, especially if this is ever going to be manufactured.

[Electr0nicus]

I would rather want the output capacitors as close as possible to the MOSFETs because this is a boost converter. This is the loop with the largest di/dt, and keeping its inductance low helps combat EMI and keeps efficiency high.

They are very close in my current layout. CP2 could be moved more to the center so the path between the GND node of CP2 and the Source of BMOS is only a few millimeters. CP2 experiences the most ripple current, as it has only ESR in the order of only 5mOhm. The OS-CON electrolytic- caps have 25mOhm ESR each, and are only for better filtering, but don't experience as much ripple current as CP2. Therefore they can be further away.

RSNS needs to be as close to the controller as physically possible or you're going to get noise on your output. It also needs thermal isolation, especially if this is ever going to be manufactured.

OK I'll make a new layout with the regulator on the top and report back.

[AndyC_772]

Yes I've tried that. It shortens the RSNS leads but makes many other things worse. As your Mosfet gate drive signals getting longer and will be routed under the inductor and switching node, also the feedback trace will have to be routed directly on the bottom layer from  VOUT to the regulator on top. And that feedback trace I consider much more sensitive than the RSNS traces.

Sounds like you've thought about it carefully, and I wouldn't argue with you. Your argument is valid, and it would take a quantitative analysis to determine which is the better approach.

Based on my own experience I would, nevertheless, still put RSNS nearer to the controller, even if that means the feedback trace is longer.

The reason is that the voltage across RSNS governs the cycle-to-cycle switching points, so any noise on it will translate directly into jitter in the duty cycle of your regulator. This can add noise, both electrical and acoustic, and can make the regulator unstable under certain circumstances. Although it's low impedance at dc, the layout you have adds quite a bit of series inductance.

Noise on the feedback line does, in my experience, tend to be less of a problem. It's setting the dc operating point of the circuit, and the compensation network means the circuit responds to changes on it over a much longer time scale. In other words, its bandwidth is lower, and impulsive noise on it has a correspondingly smaller effect.

[Electr0nicus]

Ok I have altered my layout. I analyzed the best position of the LTC3786, so that the traces to the MOSFET gates, the current sense lines and the voltage feedback trace are as short as possible. This position is actually in the center of the PCB layout as you can see on the image below:



The advantages, I think this layout has, are as follows:

• wires to the current sense resistors are as short as possible and don't run beneath high current carrying GND planes.
• gate drive traces to the MOSFETs are really short, which is good  for a clean drive waveform.
• The Boost Network (for the highside N-MOSFET driver) consisting of the Boost capacitor and the Boost Diode is in close proximity to the SW- node.
• The high current path beween the MOSFETs and the output capacitors is still there

So what do you think?

Kind regards Gregor

[peter.mitchell]

Couple of quick things;
Where are you going to connect Vin, GND and Vout?
Your feedback pin, put the corner of the L up the top, and then stitch your ground plane near the caps and switch.
If not a production board, I'd strongly consider not using thermal reliefs on the switches, it's easy to rework if they don't solder correctly, and it will lower impedance and improve dissipation. Maybe on inductor too.

[Electr0nicus]

Couple of quick things;
Where are you going to connect Vin, GND and Vout?
Your feedback pin, put the corner of the L up the top, and then stitch your ground plane near the caps and switch.
If not a production board, I'd strongly consider not using thermal reliefs on the switches, it's easy to rework if they don't solder correctly, and it will lower impedance and improve dissipation. Maybe on inductor too.

At Vin, GND and Vout there will be 1x4 pinheaders.  One for Vin (2 pins Vin, 2 pins GND) and one for Vout (2 pins Vout, 2 pins GND).
As these layouts are currently only conceptual, not all components are completly routed
Yes you are right with the inductor. If i rotate it 90° the SW- node copper area will be smaller. And yes stitching the GND planes will be done later on in the routing process. But as long as you moving components  around during layouting, having lots of stitching vias will make your work much harder, as you need to move them too.
And for the hand assembled PCBs  i will omit the termals. To change that, only a few clicks are necessary in EAGLE.

[nickm]

I hate to rock the boat but I think your first layout is better.  The second one is a big U shape and the only way to keep the loop area small is to make the return path run all the way back around as a second big U. 

The biggest issue with your layouts is the grounds.  There will be high currents flowing all over your large ground plane which goes under your IC and is bad (Even worse in the second layout).  You should really control them and make 3 distinct grounds (power, analog, and the rest).  Break up your ground so that there is one power path which is big and beefy and runs directly under the outputs caps, FETs, L and input caps.  Then star your analog ground right at the ground pins of your input and output caps.  Putting a 0ohm in between your power and analog and power grounds makes it easy to isolate them in layout.  Then fill the rest of the board with ground and star that back to the input/output cap ground pins (optional).  This will garauntee that your high currents only flow where they should and everything else stays isolated and quiet.

Your analog ground could be better because its pretty broken up.  Rotate R9 180 degrees and place its pin right on the top of the IC.  Rotate that other cluster of stuff CCW 90 degrees and this will minimize the distance the grounds are from the ICs ground.

Again I think your first is pretty good, just get your grounds controlled, everything tighter and you should be good.

[Hamed_ta]

Hi

Is there any update on your job ?

[Hamed_ta]

can anyone check this too ?

https://www.eevblog.com/forum/projects/ltc3786-3v-to-18v-boost-converter/msg2783694/#msg2783694