Level-translate the output of a TCXO crystal oscillator module

[floobydust]

I need to level-translate the output of a 10MHz crystal oscillator module.
These things are a bit odd, the module runs off 3VDC and outputs "clipped sine wave, DC-cut, 0.8Vpp"
TCXO oscillator module ECS VC-TCXO-39SM 10MHz datasheet pdf

It needs to feed a frequency counter IC 5V CMOS with 3V/0.8V logic levels.

I could try a transistor amplifier or logic gates but not sure.

[Alex Nikitin]

I need to level-translate the output of a 10MHz crystal oscillator module.
These things are a bit odd, the module runs off 3VDC and outputs "clipped sine wave, DC-cut, 0.8Vpp"
TCXO oscillator module ECS VC-TCXO-39SM 10MHz datasheet pdf

It needs to feed a frequency counter IC 5V CMOS with 3V/0.8V logic levels.

I could try a transistor amplifier or logic gates but not sure.

A good way to do it is to use a suitable fast comparator, something like LT6752, for example.

Cheers

Alex

[hcglitte]

I have done this with an unbuffered inverter with a feedback resistor.

http://www.taitien.com/wp-content/uploads/2015/12/AP20100105-Utilize-Clipped-Sine-Waveform-in-Circuit-Design.pdf

[Alex Nikitin]

I have done this with an unbuffered inverter with a feedback resistor.

http://www.taitien.com/wp-content/uploads/2015/12/AP20100105-Utilize-Clipped-Sine-Waveform-in-Circuit-Design.pdf

The problem with a "simple" approach is that you don't know how much jitter/phase noise you add to the signal. And usually the point of using an oscillator with a clipped sine output is to get a low phase noise.

Cheers

Alex

[BrianHG]

Just following the example 74HC04 illustration in the .pdf is fine.  You only need a single 74HC04 gate in a sot23-5 package, like this guy:
https://www.digikey.com/product-detail/en/fairchild-on-semiconductor/NC7S04M5X/NC7S04M5XCT-ND/673380
Just power the 04 inverter with the voltage you want to drive your logic at.

[DaJMasta]

A "DC-cut" clipped sign would be.... just the positive component of an actually 1.6Vpp AC waveform?  In that case, maybe just a fet amplifier and you have your pulse.  I guess that would make the inverter (or Schmitt trigger inverter) a viable option too.


It really does seem like a strange output, it would be more useful in my mind to just have a 1.6Vpp AC output, because then you have enough swing to get on either side of either logic level threshold if you just apply a DC bias.

[floobydust]

The osc module has a small output 0.8Vpp and apparently it's standard for many crystal oscillator manufacturers.

The Taitien app note advises using a 74HC04 with feedback resistor.
I see datasheets saying:
Buffered   CMOS 70%/30% Vcc logic-levels -need a 2V swing
Unbuffered CMOS 80%/20% Vcc logic-levels -need a 3V swing

I have 0.8Vpp available. I think this is not enough to swing a CMOS gate strongly?


The ICM7216D freq. counter IC has an internal Pierce oscillator (inverter), I thought I'd try using it. Maybe similar to 'HCU04. Connected the osc. module output to the XTAL input, leaving 22MEG feedback resistor. It works but not stable, any loading with scope probe draws it down and the counter stops. A lot of noise and jitter, it's basically a Theremin 

NC7SZU04 TinyLogic UHS Unbuffered Inverter
NC7S04 TinyLogic HS

I popped the module lid and internally, before the output capacitor, it's a mashed sine wave hitting the 3V rail.
Any loading distorts the waveform, so this must be pretty close to the raw TCXO oscillator output.

[ConKbot]

While definitely not required, and expensive for what is is (comparator and buffer, bit of filtering) http://www.linear.com/product/LTC6957-1 or the other -x variants depending on what you want for outputs are good for just this sort of thing.  The datasheet shows how to interface to almost any clock signal you could have come in, the inputs are self biasing, so you can AC couple them and feed pretty low level Vp-p signals of whatever form you have in and it will work.  For the section where they are talking about slew-rates for determining what filter setting to use, remember that the clipped sine will have a higher slew-rate at the transition than a non-clipped sine at the same Vp-p value.

[BrianHG]

ok, if you must, just use a 2n3904, 2k pull-up-resistor on the collector, 100k or so pullup on the base & a 100pf or so series cap & 1k resistor going to you TCXO unit.  This will make an inverted amplified wave up to the point of it being just about square.  Tuning the pull-up resistors will further square things off.

Obviously, the collector is the output.....

[floobydust]

Thanks everyone for the ideas.

The challenge seems to be getting enough amplitude to achieve logic 1, 0 for the CMOS gate input (in the freq. counter IC).
Confusing because (freq. counter IC built-in) Pierce oscillator is a CMOS inverter operating in linear fashion.

I tried a JFET and also a BJT preamp. Much less sensitive to loading but the voltage gain is low, best a bit over 2 so 0.8Vpp became 2Vpp and still low for a CMOS inverter or the freq. counter IC input.

If I add a couple 4049UBE inverters after the preamp, the signal is a strong sine wave 4Vpp and the freq. counter IC buys that.


The LTC6957-3 is a 3.3V part so I'd need another Vreg, and VOH maybe too low at 3.2V, for the 5V freq. counter IC.

Was looking around and found this Tinylogic SN74LVC1GX04 which looks interesting.
This has a lot of inverters for gain and squaring up a sine-wave.

[pigrew]

I'm working on nearly the same circuit, and am equally confused.

I've seen two classes of designs:

(1) The oscillator manufacturers suggest using an inverter with a large resistor as feedback. Some split the resistor into two halves and add a filter capacitor to ground between them, providing a more stable load to the XO.

(2) Others use a high-speed comparator. For example the HP 33120A and 33220A frequency reference inputs do this. I don't know about other instruments.

For my use, low jitter is not important, so I'll use an inverter with feedback. The different between the datasheet (V_IH - V_IL) isn't so important, and does not need to be more than the peak-peak of the input. This is because the inverter actually has a very small (V_IH - V_IL). The datasheet's values are guard-bands due to process and temperature variation. This website from Johns Hopkins has a nice image showing the threshold voltage variation of different devices.

The inverter in the circuit will self-bias to hold the input at very close to the threshold voltage of the inverter with the 0.8 Vpk-pk input being larger than the actual (V_IH-V_IL) of the inverter.

Note that Schmitt trigger inverters should not be use since they have hysteresis often > 1V. Comparators with Schmitt trigers are reasonable since they usually have hysteresis much less than the input's pk-pk voltage.

[floobydust]

Here is what worked for me.

The VCTXO oscillator module outputs a "clipped sine wave, DC-cut, 0.8Vpp" which means AC coupled output.
The module has an internal coupling capacitor in series with the output, so I used a DC-biased Schmitt trigger to square it up. It all runs off 3V and enough drive for the 5V counter.

[David Hess]

Phase noise usually does not matter and may actually desirable in frequency counter gate timing to prevent synchronization.

The simple data slicer configuration of a comparator will adapt a poorly controlled input into a pulse output.  This might be desirable if you do not want the output duty cycle varying too much.

Single gate amplifiers have very poor power supply rejection but are usually free.  Technically I guess you are suppose to use an unbuffered gate but I have never had problems with HC logic in this application.  Maybe faster CMOS logic would be a problem.

[pigrew]

Here is what worked for me.

The VCTXO oscillator module outputs a "clipped sine wave, DC-cut, 0.8Vpp" which means AC coupled output.
The module has an internal coupling capacitor in series with the output, so I used a DC-biased Schmitt trigger to square it up. It all runs off 3V and enough drive for the 5V counter.

Thanks for posting your schematic. My application is to interface with 5V logic, so I have to use a different logic family. Based on David Hess's comment, perhaps I should have used an unbuffered inverter. I already ordered a buffered inverter, but in the future I think I would use the SN74LVC1GX04 which you  mentioned above.

I'm confused about the "10kohm || 10pF" +/- 10% specified in the datasheet. I interpret that as a requirement of a 10k load, or else bad things may happen. However, all of the schematics I found (google image search) show only a 510k or 1 Mohm load resistor, so maybe it doesn't matter so much in practice. Your schematic shows a 5 kohm load, so perhaps it's overstressing the TCXO.

I'm attaching my current circuit layout. I changed one of the feedback resistors to 10kohm to try to present the proper load. I'm guessing that the capacitance is close to the desired value (the inverter is ~6 pF, plus a bit of parasitics throughout the board). Based on simulations, the circuit reaches equilibrium after about 5 ms.

[floobydust]

At work, these osc modules they were throwing out in the garbage, so this is why I used it.
Inside the VTXCO, a 10MHz crystal, COB IC and series output capacitor.

In all likelyhood, it's just 4049UBE stages for the oscillator and output.
I did not see the output amplitude drop with 5k ohm load, so I left it alone. It's not the raw crystal oscillator but rather an analog buffered output.

When I used unbuffered gate(s) the amplitude went up but still a sinewave with slow enough edges and I got chatter in the counter's input gate. Then I decided to use a Schmitt trigger to square it up.
At some point, the sine to square conversion has to take place.

I wondered if your circuit might not work due to the osc module's output impedance? I think if it's low (<<10k), R2 may not do anything.

[xaxaxa]

PL133-37 clock buffer can accept clipped sine wave input, and phase noise is reasonable at -100dBc at 30Hz offset.

[Leo Bodnar]

PL133-37 residual phase noise is much lower. -100dBc/Hz at 30Hz is the Micrel's source phase noise. 
PL133-37's noise will probably be around -130..-140 mark.
Leo

PL133-37 clock buffer can accept clipped sine wave input, and phase noise is reasonable at -100dBc at 30Hz offset.

[Leo Bodnar]

I have measured PL133-37 residual PN a few days ago - it is about -143dBc/Hz at 30Hz offset with 10MHz carrier.
-150dBc/Hz at 100Hz
-160dBc/Hz at 1kHz+
Not the sharpest tool in the box but cheap and cheerful.
Leo

PL133-37 residual phase noise is much lower. -100dBc/Hz at 30Hz is the Micrel's source phase noise. 
PL133-37's noise will probably be around -130..-140 mark.
Leo

PL133-37 clock buffer can accept clipped sine wave input, and phase noise is reasonable at -100dBc at 30Hz offset.

[nick_d]

Regarding buffered vs unbuffered. If you ordered the 1G04 then it's in a pretty recent CMOS technology so it will be extremely fast. In that case, you can get away with buffered for this sort of thing. And so you will not need as big an input swing. What the buffering does is simply increase the gain of the inverting amp, by putting more inverting amps in series -- each one will have a gain of say 10 to 100 so with 3 of them in series you have a gain of 1000 to 1000000 approx. This is enough to cause clipping and give you a square wave which is what you want. The reason you would use the unbuffered amp is when you're concerned about the delay through the extra 2 gates, causing instability in your feedback network. That's unlikely to be a problem here. I would have to analyze the proposed circuit to be sure. But if you are concerned, you can make your own buffered amp with 3 x unbuffered and tap the feedback from the first stage.
cheers, NIck

[Leo Bodnar]

These days you might want to use something like http://www.ti.com/lit/ds/symlink/sn74lvc1gx04.pdf
Leo

if you are concerned, you can make your own buffered amp with 3 x unbuffered and tap the feedback from the first stage.