Here's my take on the undervoltage lockout circuit theme. This is still a work in progress, designed to fix my home intruder alarm system which currently runs its backup battery down to death if a power cut lasts too long. It uses a 12V, 1.2 A-hr valve regulated lead acid cell. There is one pair of leads connecting it to the panel, it appears to be used in float mode.
I apologise for the scruffy hand-drawn circuit, but if you can read it you will see an LM10 configured as a comparator, controlling a BUZ11A FET in 'backwards' mode as the switch (since I had one handy). The turn-off threshold is about 10.9V, the turn-on about 12.1V. Assume the FET is off to start with. The charge current from the alarm panel flows through the body diode of the FET and the battery charges. When it reaches 12.1V terminal voltage, the FET turns on, shorting out the diode - the battery now sees pretty much the full original charging voltage, and operates in float mode.
Now assume the mains supply fails and charge power is removed. The battery supplies load current through the on FET, with the LM10 and sensing network taking about 300uA additional load. When the battery discharges to 10.9V, the LM10 turns the FET off. The voltage at the FET drain now starts to rise toward +10.9V (assuming there is some capacitance in the panel to slow it down a bit) and when it reaches about 6V or so the CMOS Schmidt trigger switches, driving the outputs of the 4 paralleled stages which power the LM10 low. The LM10 and sensing network are now powered off, and the current drain from the battery is essentially zero. Even if the battery voltage recovers above 12.1V (unlikely) the FET cannot be turned on again. The only way to reset it is to apply charging power to the FET drain. This switches the CMOS Schmidt trigger back, reapplies power to the LM10, and once the battery charges to 12.1V, turns the FET on again.
The 1k0 resistor in series with CD40106 pin 1 is protection to limit the pin's input current when the FET drain voltage is negative of it's source (FET off, battery charging from the alarm panel through the body diode). The 4u7 capacitor on the LM10 supply is there to slow the rate of voltage rise so that the LM10 has time to turn on (which takes about 150us) and drive its output low before the LM10 supply reaches the FET threshold voltage. The LM10 output seems to always power up high at turn-on. With 100nF here, the FET is glitched on for about 250us - this doesn't seem to do any harm, but I thought it best to avoid it.
The circuit also acts as a 'battery seal', since it will power up in the off state when connected to the battery. The circuit is only really suitable for 12V batteries, as although the LM10 will take 40V, neither the CMOS VDD-max nor the FET VGS-max allow it.
Any comments?