Glad you liked it - I haven't weighed the box and I'm terrible at guessing weights, but it is pretty heavy for its size, with a lot of solid metal! Ground equipment for space installations is usually rack-mount stuff that looks much more "normal", as it doesn't have to put up with unusual environmental conditions; everything about the packaging on this one, based on lots of photos of other space hardware, says "I'm made for spaceflight". Can't be 100% sure of course, but my best guess is that other copies of this are on a communications satellite somewhere (or that this was a prototype for a design which ended up on a satellite).
Ok, here's #2.
Space Micro microwave transmitterThese few boards came in a set (for gold scrap), and all appear from the labeling to come from the same unit: a "µXTx"-model X-band (~8-12 Ghz) microwave transmitter, which takes in a digital data stream and outputs modulated & amplified RF directly to an antenna.
Here's a datasheet for a very similar model, except these boards date from about 2008-2011. The manufacturer is Space Micro, a commercial supplier of electronics & optics for satellites. These are not COTS parts meant for low-cost cubesats where the lifetimes are measured in weeks or months though; the Space Micro products seem to be mostly radiation-hardened high-reliability stuff meant to work for a decade+ (that translates to more-interesting parts for us to look at!).
Digital Board
To see where the data starts its journey, let's look at the digital board first. The digital data stream most likely enters from outside the box into the connector at the bottom-left. This looks a lot like a specific connector series made by Samtec that I've used before, which has impedance-controlled contact geometry and keeps a ground plane present at all times, with a flat plate on the male side and a bunch of mating contacts on the female side - this is designed specifically for, and works great for, carrying high-speed digital signals.
Here's a link to the Samtec Q-strip series, where you can see some images of what I'm talking about.
This data makes its way to the Actel ProASIC3E FPGA that does almost all the digital processing on this board:
There's also a mystery ASIC to help it out - the "LDPC" in the name might stand for
"Low-Density Parity Check" coding. I don't understand exactly how they work, but they seem to find a lot of use in communications, which supports the idea of this ASIC being a hardware accelerator. You can
also read an article here on its implementation in an ASIC for multi-Gbps data, which again seems pretty applicable here.
The FPGA also has access to a 128K x 8 EEPROM (5962-3826716). I'm not sure exactly what this is storing; can't imagine it's the FPGA configuration but I don't see a dedicated EEPROM for that, or it could also be program code for a soft processor used in the FPGA.
This system is an SDR (Software-Defined Radio): the modulation is all done digitally on the FPGA, which then drives a DAC to produce the modulated IF signal. Flexibility is very important in space applications (as you can't just pop the cover and swap a board once it's in orbit...if you're not a high-priority space telescope, that is) and the datasheet for the uXTx transmitter mentions many aspects that are configurable in the field, such as modulation scheme - this is how that's done.
The DAC itself is a
Texas Instruments DAC5675A, which does an impressive 14 bits @ 400 Msps. This is fast enough, if run at full speed, to produce a modulated IF output in the 10-100 Mhz frequency range.
You can also see an interesting pattern here, which is repeated throughout these boards: notice that the footprint on the board is meant for the
much wider ceramic & gold package, of the rad-hard space-grade part you can view here. But they've used a little daughterboard which adapts the this footprint to the infinitely-cheaper commercial plastic-packaged version of the DAC5675A - this strongly suggests that these boards were an early-stage prototype/bench-evaluation copy, definitely not a model meant for environmental testing or flight. When you might blow up some chips and just want to test the basic design functionality in a climate-controlled lab, why waste thousands of dollars per IC?
The DAC gets its clock from the modulator board (we'll look at that next), which provides a reference clock so that all the clock sources are synchronized. This clock enters through one of the two coax connectors, gets converted to LVDS by a DS90LV031A, and sent directly to the DAC. A second copy of the incoming clock is also converted to LVDS and sent to the FPGA, but first it goes through the winding delay line at the left here. You can see the multiple groups of three resistor footprints: at each one, the path can be tuned to be slightly longer or shorter (therefore tuning the delay time) by choosing whether the two "longer-path" or the one "shorter bypass path" resistor is populated.
The FPGA can't change change the output data to the DAC right at the DAC's clock edge(s): it needs to change the data somewhere in the middle of the clock cycle, to meet setup and hold time requirements. I believe that timing constraint is being enforced here by this hard-wired delay, to provide the FPGA with a clock that can be used to synchronize the output data to the DAC.
I did a similar thing about 12 years ago, but with an ADC sending a few lanes of DDR serial data to a Spartan 6 FPGA. The reference implementation there from TI/Xilinx used a tunable delay element built into the FPGA's I/O block, which was automatically tuned at startup by setting a test pattern, finding the delay values that would align the data with both clock edges, and then setting a final delay value halfway in between those two for maximum headroom. That's much harder to pull off with outgoing rather than incoming data, though, plus I don't know if this rad-hard FPGA even has a tuneable delay; it also adds extra complexity and room for things to go wrong, if the desired clock delay is a known quantity and can be determined ahead of time.
Anyways, the DAC's output now drives a coax output via a transformer that does the differential-to-single-ended conversion (top-right in the photo below). You can also see the linear regulator (MSK 5900RH) which likely provides a low-noise supply for the DAC.
Digital board by
D Straney, on Flickr
Finally, there's an LM139 quad comparator. I don't know what this does: maybe it monitors RFPA temperature for the FPGA? (We'll see that later) From the connections, and lack of resistors on the bottom side of the board below the comparator, it looks like only one of the comparators is actually used.
Modulator BoardThis board generates the reference clock for the digital board, and up-converts the digitally-generated IF signal to the X-band output frequency.
It's a sign of how far miniaturization has come, that most of the complex RF functionality (VCOs, mixers, etc.) is stuffed into a few MMICs in a row along the bottom...
...while the largest component by far is just a passive quadrature coupler, which splits a signal into in-phase and 90-degree-shifted components:
I really have no idea why this particular part is used; the MITEQ catalog lists it as supporting 50 - 110 Mhz @ 250W average, but it never sees even anywhere near a single watt on this board. With such a low frequency range I can't imagine the coupler uses distributed elements within, which would make it physically large no matter the power level...but it's also very flat, so who knows.
Anyways, things begin at an empty footprint, which I'm 99% sure used to hold a reference oscillator module
like the one from the Rocketdyne CPU board:
The chip in charge of generating the LO signal for upconversion is this Peregrine PE9763, which contains all the functionality of a frequency synthesizer, minus the VCO itself:
Its parallel control inputs probably get set by the FPGA.
If you look at how everything connects, it all makes sense:
The PE9673 frequency synthesizer maxes out at 3.2 Ghz, but the design here takes advantage of the fact that the VCO has a "divided-by-2" output to synthesize a higher LO frequency. It still doesn't entirely make sense, as the VCO (Hittite/Analog Devices HMC510) has an ~8.5-9.5 Ghz range, which is still >3.2 Ghz when divided by 2. Maybe I missed something when tracing the connections. Either way, the DAC gets a divided-by-16 copy of the VCO as its clock. The upconverted RF output goes out to the power amplifier on a different coax connector.
The long metal-boxed filter down the side of the board seems to be anti-aliasing for the DAC. The input would be at the port marked "output" on the filter, but as it's a passive device with the same impedance at input and output ports, the input and output are going to be interchangeable anyways - the actual filter schematic inside is almost definitely perfectly symmetric.
The one uncertain part is the mystery device with a custom-looking part number here, which I haven't been able to find any references to. It has DC biasing resistors connected to all the RF signals that go through it, and given its place in the circuit, the only thing that makes sense in context is if it's a dual amplifier (see schematic above).
I have no idea why it would be necessary to make a custom package with two RF amplifiers here, as this doesn't seem like a particularly unusual need, or space-constrained in any way. Let me know if you've got better ideas. Maybe I'll pop the lid on this device and have a look inside to confirm.
RF Power AmplifierThe final board in the signal chain here is the power amplifier, which boosts the modulated RF to a few watts for transmission through the external antenna.
You can see that it's meant to dissipate some real power, as the base plate is a solid metal block, which the power transistors are connected to directly.
Things start at the input connector, where the modulated RF signal goes through a couple stages of preliminary amplification (HMC346 & HMC441 amplifiers)...
...before driving the first dedicated power transistor:
The output stage consists of two paralleled transistors sharing the output power: the signal gets split in half through a branchline coupler, fed to the two larger power transistors, and then re-combined through another branchline coupler.
Other features of the output stage, visible in this photo:
- A directional coupler (the upside-down "U" at the left) picks off a small portion of the output signal. The forward-power signal from the coupler goes through a resistive attenuator, and then into a mystery part (large gold box at bottom-left). This mystery box also connects (from its right side) to one of the discrete-wire connections that bring DC power to the RFPA. Because the connections to this second signal are not set up at all for high frequencies, it must be DC of some kind - my best guess is that the "mystery part" is a power detector, used to monitor the output power level.
- A circulator (silver box at left, likely with resistive termination inside) to keep out reflected power from the filter (discussed next) & antenna.
- Output filtering, just before the coax connector (top-left corner): the standout feature here is all the little semicircular wideband quarter-wave stubs. These are normally used as an RF short at their quarter-wavelength frequency to block RF on DC control traces - you can see the ones used for this purpose at the bottom-right & top-right of the photo, on the DC bias lines for the power transistors. However, here, their in-line placement with the RF signal, and the small size compared to the branchline coupler, makes me think they're supposed to suppress a specific harmonic frequency in the output. They look roughly 1/3 to 1/4 the size of the DC bias ones at the bottom right, so they're probably supposed to block the 3rd or 4th harmonic of the output frequency. The branchline couplers are much larger, but the lines in these don't have to be 1/4 wavelength: they can be made any odd multiple of 1/4 wavelength, whatever makes the layout easiest (with some bandwidth penalties I think).
A temperature sensor lives next to one of the output-stage transistors, to monitor their temperature. I'm not sure exactly where on the other boards this is monitored.
One thing I didn't have any luck with, was finding out how the power transistor biasing was done. Most of the time you can't just put a constant DC voltage or current on the gate or base, as the threshold voltage or beta will change wildly with temperature and send the DC operating point into all kinds of undesirable (too-low & too-high) regions. The input bias connections on this board just went straight through filters to off-board wires, and none of the other boards had circuitry that could be doing collector-current-based bias control or anything similar. Then again, a lot of these types of amplifiers I think are full-on ICs these days, rather than just a plain transistor, and so could easily have their own bias-control circuitry on-chip (this is not my field at all so please correct me if I'm wrong).
Power BoardThe last board here is the under-appreciated power supply, which creates all the low supply voltages (+10V, +/- 5V, +3.3V, +2.5V, +1.5V) for the other boards, generated from an external 28VDC input bus.
Most of this board is off-the-shelf DC-DC converter and EMI filter modules; we can look inside those later.
There's also some linear regulators, which create the lower voltages:
Here's what's going on circuitry-wise on this board, with details omitted where they don't add anything:
The interesting bits on this board are...
1. At the output of the +10V supply: really a +/-5V supply, with the -5V referred to ground. I'm guessing the +10V is used for the RFPA.
These components are in the "input power present indication" box on the schematic. A TL431 and optocoupler produce a 2.5V digital output which is high when the input power is above a certain voltage threshold: this is probably sent to the FPGA, and used to tell when the input voltage is starting to sag for some reason.
2. Behind the linear regulators:
The two ICs here are a quad op-amp, and a quad AND gate. An op-amp and two AND gates are used, as described on the schematic, to wait for the +3.3V supply to be present and also a "high" control signal from the FPGA, to activate the +10V supply. This further supports the idea that the +10V supply powers the RFPA.
The other 3 op-amps are used in an interesting way: each subtracts one voltage rail from another, and the results travel off-board via a set of discrete wires. My best guess here is that these wires go to an external connector on the box, and are used during testing. During environmental testing of a piece of space equipment, you'd want to be able to make sure that all the internal power supplies are working correctly even when the box is being baked or shaken, and so monitoring the internal supply voltages would be important. Looking at linear combinations of the supply voltages lets you verify this with fewer wires, though, than if you just ran every internal supply voltage to the connector: the (+2.5V) - (+1.5V) output, for example, (TP27) will always read about +1V if both supplies are working correctly. If the measurement is significantly different than +1V, it doesn't tell you whether the 2.5V or the 1.5V supply is failing, but you know that something is wrong.
With the SOIC packages above, you can see the same type of "dual prototyping & flight" component footprints that I mentioned before with the DAC, on the digital board. Notice how there are standard plastic SOICs populated, the same as I'd buy from Digi-Key - but the pads extend much further, with a little bit of soldermask dividing the two sections of each pad. This is likely so that rad-hard flight-qualified ceramic flatpack versions of these same ICs, which are much larger, can be populated on non-prototype versions of the boards. If you go back and look at the two optoisolators on the power board, you can see a similar thing: next to each plastic optoisolator is an unused slightly strange-shaped footprint, meant for a
space-grade optoisolator in a package like this one.
Anyways, that was a whole lot of text - hope that was an interesting look inside some real satellite hardware.
Home
Help
Search
Login
Register
