Miscroscope view of a transistor

[pdu]

Hello everyone,

I was recently able to use my university's microscope to observe some ICs (it is a microscope used for materials ananlysis. I am not studying materials or electronics by the way). One of the component was a BS108 MOSFET in a metal can. I am currently trying to analyse its structure but I am having some difficulties and I hope you can help me   

First, here is a shot of the transistor:


I was able, using a mutimeter and the datasheet, to identify some of the pins/wires.

Here is a drawing I made to make things clearer:


Finally, some datasheet (for example this one, pdf: https://www.bucek.name/pdf/bs108.pdf) describes it as a vertical n-channel enhancement mode DMOS. One of my resource gives a structure for this type of transistor: http://www.circuitstoday.com/double-diffused-mos-dmos

So, I made this cross section view of the transistor but I am not sure that I have the correct structure:



I am sure about the position of the gate, the source and the case (datasheet + multimeter). But I am not the sure of the shape of the cross section, the structure (letters) and the type of material / regions (numbers). Are my guesses corrects ? Do you have any idea ?

Thank you 

PDU

PS: It's my first time posting here, so I am not sure this is the right place. Tell me if anything is wrong (image size, image host, forum,...) 

[strawberry]

Layers should be more or less same high , otherwise coating will get uneven thickness

[tpowell1830]

Just a swag, but my guess is C is the gate, unsure of others... The bonding wire, since it has a ball, is definitely gold.

[Wimberleytech]

The drain (n+) is in the center.  The source (n+) is the outer region.  The substrate is p-.  The gate is on top.  I do not show the oxide in this simple sketch.

[Wimberleytech]

The drain (n+) is in the center.  The source (n+) is the outer region.  The substrate is p-.  The gate is on top.  I do not show the oxide in this simple sketch.

It is possible that I have the drain and source flipped.

[pdu]

Hi,

Thank you everybody for your answers 

Layers should be more or less same high , otherwise coating will get uneven thickness

Do you mean semiconductor layers or all of them (including gate oxyde and gate). ?

Just a swag, but my guess is C is the gate, unsure of others... The bonding wire, since it has a ball, is definitely gold.

I don't think that C is the gate as I was actually able to identify it as the source with a multimeter in continuity testing mode. Well, more specifically, since you can see with the naked eye which wire is broken I was able to determine that the pin with no wire was the source pin.
You're right, it's probably gold. This would match the goldish color of the wire. Only gold wires have a ball ? Good to know !

The drain (n+) is in the center.  The source (n+) is the outer region.  The substrate is p-.  The gate is on top.  I do not show the oxide in this simple sketch.

It is possible that I have the drain and source flipped.

Yeah, the source is definitely in the middle. Thanks for the position of the (p-) material. Would the following cross-section be more correct according to you ?


In this case, I don't really understand how the case can be connected to the drain (there is a connection between the external drain pin and the case). Also, it would correspond to the double-diffused MOS structure but not to the vertical double-diffused MOS structured advertised in one of the datasheet (if I'm not mistaken). Or maybe different manufacturer makes the same component with different structures.

Sorry if I appear to be a bit stubborn,  I am really trying to understand things

PDU

[Wimberleytech]

After further study, I change my view on the structure of this device.  In an old Philips datasheet, it is described as DMOS.  The drain is the back side eutectic bonded to the leadframe.  I suspect it looks like this

[rfeecs]

You can only guess by looking at the microscope picture.  All you can see is the metal and dielectric pattern on the top of the die.  Different thickness dielectric makes different colors.

Based on the above picture of the vertical DMOS structure and the electrode pattern you determined of source in the middle, a guess might look something like this:

[tpowell1830]

Hi,

Thank you everybody for your answers 

Just a swag, but my guess is C is the gate, unsure of others... The bonding wire, since it has a ball, is definitely gold.

I don't think that C is the gate as I was actually able to identify it as the source with a multimeter in continuity testing mode. Well, more specifically, since you can see with the naked eye which wire is broken I was able to determine that the pin with no wire was the source pin.
You're right, it's probably gold. This would match the goldish color of the wire. Only gold wires have a ball ? Good to know !

Yes, I spent many years working with wire bonding machines and the ball is created by a high voltage spark on the end of the gold wire that creates the ball by voltage and timing control circuitry. Aluminum wire is wedge bonding, meaning no ball.

[pdu]

Hi,
Sorry for the long time without any post.

@tpowell1830: I have also read that copper can be used for wirebonding. Do you know if this also results in a wedge as for aluminium ?

@rfeecs & Wimberleytech: In both of your drawings, the hatched regions correspond to the metal conducting layer ?

@rfeecs: I know that I can only guess so much by looking at a picture, unfortunatelly. What would make you think that the n+ regions is split in two ? (And what would be the purpose?) I've seen some pictures with only one n+ region. For example this one (from circuitstoday.com, used for my first schema):

Unfortunatelly I can't get too much information out of the colour as the white balance was a little bit off when I took the pictures.

[Wimberleytech]

@rfeecs & Wimberleytech: In both of your drawings, the hatched regions correspond to the metal conducting layer ?

Yes

[tpowell1830]

Hi,
Sorry for the long time without any post.

@tpowell1830: I have also read that copper can be used for wirebonding. Do you know if this also results in a wedge as for aluminium ?

@rfeecs & Wimberleytech: In both of your drawings, the hatched regions correspond to the metal conducting layer ?

@rfeecs: I know that I can only guess so much by looking at a picture, unfortunatelly. What would make you think that the n+ regions is split in two ? (And what would be the purpose?) I've seen some pictures with only one n+ region. For example this one (from circuitstoday.com, used for my first schema):

Unfortunatelly I can't get too much information out of the colour as the white balance was a little bit off when I took the pictures.

I have no experience with copper in wirebonding, sorry. We only used gold and aluminum. One of the problems is the hardness of materials on top of the silicon, it will crack, like glass. So we exclusively used gold on top of the ASICs, and aluminum to make connections between the substrate pads.

[rfeecs]

@rfeecs: I know that I can only guess so much by looking at a picture, unfortunatelly. What would make you think that the n+ regions is split in two ? (And what would be the purpose?) I've seen some pictures with only one n+ region. For example this one (from circuitstoday.com, used for my first schema):

The n+ appears split because the source contact connects to both the n+ and the p region.  This shorts the parasitic npn transistor and forms the body diode.

Actually I was trying to fit the layout to your picture.  The n+ would form a ring under the source pad.