WaveyDipole
I'm looking at the Mega 2560 wiring. Is there any reason not use 24 pins on the two row header at the end? It's been a couple of years since I looked at the board details, but a 24 pin ribbon cable on the 2 x 18 header at the end feeding the GPIB bus connectors via a ribbon cable seems a lot cleaner than the current wiring for the 2560. Though perhaps not as convenient if one wants to use a stock LCD display.
Is there a pin assignment constraint that prevents doing that? A
Since the possibility of adding a touch display was mentioned, I looked into the displays available for the Mega and it turned out that the touch display uses that two row header. On the other hand, shields tend to use the side connectors and the basic two row text display can make use of any available pins. There was no possible solution that could satisfy keeping both the two row connector and sufficient pins for shields free. I was also unsure about using the pins designated for the SPI bus for PCINTs (50-53) so in the end I decided to go with leaving the end connector free. However, *theoretically* there is no reason that the GPIB controls pins could not be confined to the two-row header. On the UNO, pins 11 and 12 are also allocated to MOSI and MISO but using them for GPIB control seems to have had no ill effect on being able to use the SPI connector to program the board with an AVR programmer. I therefore suspect that there should be no problem using pins 50-53, but not having tested it, at this time I can't say for sure.
The port layout is still a bit awkward as each register port corresponds to 4 pins on each row so to use one port you have to use 4 pins across two rows rather than 8 consecutive pins on one row. Since a couple of pins with PCINTs are required, the GPIB control pins would perhaps have to occupy the left hand side (39-53 and 38-52) and the remaining pins could be used for other purposes including to control GPIB Bus driver chips. I could implement the code so that the current layout and the two row connector layout are selectable by means of a #define directive providing the user/developer with the option to use either.
On another note, regarding the ESP32, it seems that the ESP32 board documentation makes no mention of PCINTs or pin register ports. Interrupt handling is provided but seems to be implemented somewhat differently and it seems that pins would have to be managed using pinMode(), digitalWrite() and digitalRead() methods which are slower than direct port manipulation that is being presently used to maximise performance. The current code would therefore need a substantial re-write and performance may be impacted somewhat, but I do intend to do some work on it in due course.
For the present, I would like to focus on the Mega and complete what I have planned as well as include any further suggestions.
With regards to that, I found the multiple GPIB buses idea interesting. Theoretically one should be able to accommodate up to 3 GPIB ports on the mega with a handful of pins to spare. Whether that would mean having 3 separate GPIB buses or just one bus with 3 ports I'm not yet sure, but it would certainly allow significantly more instruments to be connected. If this is something that is likely to be useful, then I will consider adding that as a feature. It does have an impact on the use of the two row header so implementation would need some careful thought, especially if the flexibility of using different layouts as discussed above is to be maintained.