so the input signal would be attenuated with additional amplifiers (i.e. to have a gain of +-0.5, +-0.4, +-0.3 ... ) and each of these inverted/non inverted amplifiers pairs would be connected to a switch connected to point A so that at any time half of the amplifiers would be connected to point A?'
So for instance the amplifiers of +1, -0.5, -0.4, 0.3 could be connected while 0.4, -1, +0.5, -0.3 would be disconnected (i did not follow the timing diagrams here but is my reasoning correct)?
This method demands many op amps.
and in addition to this the reference signal would be fed into the frequency divider block to time all the switches, which seems easy enough in a CPLD.