analog pulse shaping strategy question

[john23]

Hello i need to convert a 0-3.3V 120ns 500ns period pulse into -2v to -5V pulse to turn on and off CGHV1A250F.
A 100pF load is the load which represents the gate of the CGHV1A250F.
I got the circuit shown below ,but its very odd.
I need to control the upper level lower level and keep the output pulse as square as possible.
Is there some new circuit configuration you could reccomend me to use instead the circuit i got?
Thanks.
https://pdf1.alldatasheetde.com/datasheet-pdf/download/1673867/WOLFSPEED/CGHV1A250F.html

[CosteC]

I am not sure why PNP transistors? NPN are usually bit faster. Negative voltages does not force use of PNPs.
I would not parallel two different types of transistors. My gut feeling is it will be hard to control (last stage)

For very rectangular pulse shape lot of bandwidth is needed. Possibly faster transistors are the solution. I would also suggest using circuits not saturating transistors - de-saturation takes time and is not repeatable.

[moffy]

This could work, it uses the PNP to level shift and U1 for drive, if you need more output drive you can always parallel the inverters.

[magic]

This looks like the easiest solution indeed. In fact, only one inverter gate is needed because the original circuit inverts the pulse (high state becomes low and vice versa).

74LVC1G04 is a tiny chip with one CMOS inverter gate. There is also 74LVC2G04 for those times when two gates are needed.

[Benta]

Why not just AC couple the pulse train?
Setting initial conditions and clipping levels is easy.

[PCB.Wiz]

Hello i need to convert a 0-3.3V 120ns 500ns period pulse into -2v to -5V pulse to turn on and off CGHV1A250F.

That CGHV1A250F shows as a $800+ fancy 5GHz RF MOSFET
What are you trying to do here, exactly ?

[john23]

Hello Costec,Very good suggestions,What higher bandwidth BJT you reccomend me to use?
Why do you say that putting them into saturation makes the BJT with lower BW?
Thanks.

[TimFox]

When researching this question, the usual term of art to search is "level shifting", not "pulse shaping", which usually refers to issues such as rise time.

[john23]

Hello, Macom company answered my question  as shown below the astrix.
I dont understant this answer, in the end of my circuit there is a load which is supposed to represent  CGH1A250F.
I know to know how to represent it some how.
How exactly  do i suppose to interpret this answer into a simple R or C model of the load?
*************************************
"The gate capacitance you refer to below is the absolute maximum for the part.
In real operation you should never see this value.
Here is a snapshot of the gatecurrent vs. drive-up & freq.
You may see up to 2mA if operating in saturation and depending on the frequency.
This is the typ. Max stated in the DS, you may design your circuit with a little headroom for tolerances. It is also a question if you drive the device that much into saturation."

[ArdWar]

Of course they'd be confused. No one expected someone to drive a X-band RF transistor as a switch with square wave at 2Mhz.

[tggzzz]

Of course they'd be confused. No one expected someone to drive a X-band RF transistor as a switch with square wave at 2Mhz.

It may be an "off prescription use", but it isn't unknown.

For example, John Larkin at Highland Technology bemoans that such transistors' datasheets have S parameters but few specs that are of use in the time domain.

[ArdWar]

Yeah, it is still valid operating point indeed.

Just that 2MHz (500ns pulses) is way too low if it's meant to be the signal, but also way too high if it's meant to be part of gate bias sequencing or modulation.
I guess it is the latter case since OP also hinted at precise control of voltage levels. But biasing isn't usually done that fast, and usually done with either precision voltage regulator or even DAC. A too high rise/fall time might not even advisable here since the bias generator is usually immediately followed by RF blocking inductor. Sounds like great way to wreck GaN FET gate.

[john23]

Hello, could you please explain why my FET gate will be ruined from fast pulse?
What parameter in the datasheet says that?
Thanks.

"A too high rise/fall time might not even advisable here since the bias generator is usually immediately followed by RF blocking inductor. Sounds like great way to wreck GaN FET gate."

[ArdWar]

could you please explain why my FET gate will be ruined from fast pulse?

Because with such fast edges your blocking inductor and gate capacitance may ends up causing large amplitude ringing, and GaN FET gates are usually much more fragile than other types of FETs.

Anyway,
You may get much better advice here if you just tell us what you're trying to do, or at least letting us know a bit more instead of asking many piecemeal question on very specific functions that may or may not even relevant to what you're doing.
From your other questions I was assuming you're trying to make a high power RF amplifier or some sort. But frankly the details aren't quite add up, part choices are a bit weird, and feels like you *may* misunderstood some basic engineering detail that *may* lead you to some weird parameter choices.