Yes I had noticed that the bottom layer in their design did not have a slot, and yes I found it a bit odd since they other layers had it. I thought their intent was to separate the power ground from control ground to reduce noise outside the SMPS?
In what sense; control ground where? There's no AGND pin on this device (some regs have that though).
The fact that they have input and output exiting in different directions means there is an overall path across local ground loops, i.e. the ground that VIN is bypassed to is different from the ground VOUT is bypassed to. Measuring these nodes at a distance, there will be some voltage between them, that is not due strictly to the ripple on each one by itself (i.e. V(VIN, local GND) + V(VOUT, local GND) != V(VIN, VOUT)). This is probably a small effect, because ground is overall fairly dense still, despite their odd layout. Small enough you wouldn't notice it in comparison to the ripple on each node by itself.
Like, the weirdest thing about their layout is probably this:
Notice the length between GND pin and vias. Switching current flows through this path, thus the chip's internal ground is offset by the voltage drop along here.
Like this:
Now, C1 especially C/D do bypass along this path, so I'm overstating things a bit. The switching current flows between VIN/GND and SW so the common-mode isn't dropping across the full ~5nH. But it is if there's high-frequency currents flowing out of the SW node; most inductors have a high-frequency series-resonant or capacitive mode which is relevant here, and that current will drop through this full path.
So much better to use vias directly:
and remove the ground slots (what were those doing anyway, more ground is better?!).
Notice the path between pin 7 and C1D can be widened, reducing inductance a bit additionally.
Speaking of inductors -- one wonders just what they had there. I haven't seen one with that footprint before. Does it really have a ground connection -- core connection, or shield, perhaps? That might contribute noticeably to EMI: both in reducing emissions by not having the bulk of the inductor body have switching noise on it, and by increasing its capacitance, and therefore CM switching currents as mentioned above. (Which is a local effect, manageable by layout or filtering; the inductor body acting as a tiny antenna however is not, and would require shielding if it is found to be excessive.)
If you are going to use ground slots, the proper way to apply them here is to rout around the circuit, leaving it as a peninsula. VIN, VOUT, and any signals, are routed along an isthmus between the peninsula and the main board. It doesn't need to be as narrow as "isthmus" implies, indeed it should be wide to keep inductance down, but also width implies local loop currents can flow into it. More that it should be longer than it is wide, so those loop currents die out along its length. Anyway, all signals coming along this path shall be bypassed and filtered to it. This acts like a single point, and there is zero voltage across an ideal point so we've eliminated ground loop from the system. Notice also it's a three-terminal regulator: VIN, GND, VOUT (...and whatever control signals). You can't have any common mode on a common-ground system by definition, so we've again eliminated ground loop.
As for the control signals, they should be filtered as well as they can be, given their bandwidth. Here, just EN and PG need to leave the site, if at all. A ferrite bead along the isthmus, with a bypass cap at either end (100s pF to 10s nF, kinda who cares?), should be adequate filtering.
If you needed, like, some kind of data signal here -- I don't know, maybe an SPI controlled regulator? -- you might simply deal with EMI on a system level (because you can't compromise SPI bandwidth too much: usually SCLK has a maximum rise time for example, or maybe the bus is shared with other fast devices), or it can be communicated as a differential pair using data chokes to cross between ground domains (additionally, using RS-422 transmitters/receivers seems terribly overkill for this, but would certainly do the job..), preserving signal bandwidth without carrying as much ground loop noise into the bus.
Maybe a more meaningful example would be something like, a module, or "shield" if you will, that's got onboard power, and it's dirty -- they did a shitty layout and you can't fix it, it's a 3rd party module -- and it's also got, I don't know, Ethernet coming in or something. Maybe its noise can be isolated off to one side, and the signals (RMII I suppose?) carried via CMCs to the quiet side. This wouldn't address the common mode out the connector though; you'd still need some kind of grounding solution to keep noise down at the BS terminator node, more or less.
...If you don't know about typical Ethernet circuits, this probably isn't very meaningful, and that's alright. These probably aren't very meaningful examples without diagrams anyway.
In any case, the point is, even if you need to pass high-speed data along such a ground-isolation route, there are methods to do so. They might not be preferable (adding a bunch of CMCs and filtering, when the problem could likely be solved with better layout, or choice of less noisy parts), but it is possible.
Ok thank you. For the outputs, what do you think would be appropriate?
If the loads are nearby, added ESRs might not be necessary.
The isolated output might have two 10uF's, total, say, one at the rectifier, one at the chip?
5V output, if routed over some length, probably should have some damping, to terminate the PDN (power distribution network). Exact values, and spacing of bypass and bulk caps along the route, depends on where and how it's routed.
If inner plane, just some bypasses scattered about is probably fine.
If 5V just goes to a couple loads then a 3.3V LDO, a couple 10uF (total as required by the MP4576) and maybe a bulk cap will be fine. Again, exact value and placement depends on routing.
The 3.3V in turn (if applicable), depends in the same way. Choose an LDO with low GND pin current (check for a plot of I_GND vs. VIN; it can be shockingly bad on some bipolar types, or is rarely a concern on CMOS types), and check for any discussion of stability vs. ESR and C_OUT values. Modern types are designed for low ESRs so put on as much ceramic as you like. Older types require ESR within a range so you will need a bulk cap (with its ESR) to be dominant, at least near the reg's cutoff frequency (typically 10-100kHz). It's okay to have low-ESR bypasses in parallel here, as long as they don't reduce the ESR in this particular frequency range. Which means, using much less total value bypasses than bulk cap.
And so on for other supplies.
Tim
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