ADV7513 I2S No Audio

[Mario87]

Hi all,

Happy new year! Hoping someone on here can point me in the right direction as I have a feeling I must be doing something wrong...I have a project where I am pulling audio and video from a PS2 console, passing into an FPGA, upscaling & de-interlacing the video to 1080p, 60Hz then outputting to an ADV7513 and over HDMI to the screen.

The video aspect is working perfectly, no issue at all, both when the FPGA is doing heavy lifting and outputting at 1080p or when I set the FPGA to act as a simple pass-through and the video stream is the default 576i from the console. Obviously I adjust the registers within the ADV7513 accordingly for 1080p vs 576i, but I get a proper video signal on screen every time.

The issue is with the audio aspect. The console feeds the audio as I2S format to a DAC and this is where I am tapping into the audio stream, details of which are as follows...

• LRCLK = 48kHz
• MCLK = 18.43MHz (384x LRCLK)
• SCLK = 3.07MHz

From the screen captures below I took from my logic analyser the I2S format appears to be 'Left Justified' and 24-bits wide as shown in Fig 17 of the ADV7513 programming guide (snippet in the 4th image).









As such, I setup the ADV7513 audio registers as follows (based on info from page 69 to 80 of the Programming User Guide)...

• Register 0A set to binary value 00000010 / hex value 02 (Auto CTS, I2S data stream & 384x MCLK ratio)
• Register 0B set to binary value 01101110 / hex value 6E (SPDIF disabled, I2S clock latches on falling edge (see images above) and MCLK is available (not internally generated))
• Register 0C set to binary value 00000110 / hex value 06 (Use I2S stream sampling frequency, use channel status bits from I2S stream, only I2S pin 0 enabled and left justified mode (based on screen captures above)
• Register 15 set to binary value 00100000 / hex value 20 (I2S sampling frequency of 48kHz)

The last register (0x15) should not be needed as I have set register 0x0C to use the I2S stream sampling frequency, but I have tried with register 0x15 set and not set, makes no difference.

Despite configuring the registers seemingly correctly there is still no audio at all. I have tested both with the 1080p video feed and the un-tampered 576i video feed in case there was some mismatch preventing it from working. The monitor I am connected to has audio volume set to 50% and outputs audio fine when connected to my laptop.

Link to programming guide for reference... https://www.analog.com/media/en/technical-documentation/user-guides/ADV7513_Programming_Guide.pdf

Anyone have any suggestions?

[Mario87]

Ok, so looks like I may have forgotten to set register 0x02 with value 6144 (decimal) / 0x18 (hex). This is the N-parameter register and used to configure the audio clock regeneration at the sink. So now audio works with my 576i pass-thru config quite well (clear audio), but when I use my 1080p config to upscale, de-interlace, etc the audio is crackling and comes / goes.

Anyone have any thoughts on what might be happening here? With my 1080p FPGA config the audio is still just passed through at the moment, exactly as it is on the 576i config, just goes into the FPGA and straight out, so not sure why the different video stream is affecting the audio from working properly at 1080p?

Is 48kHz not a supported sampling frequency for HD video? Do I need to increase the sampling frequency up to 192kHz (4x) using a PLL or similar within the FPGA?

[moffy]

I am sorry I don't know much about HDMI, but your question is so well framed/communicated I just had to comment. The only slight idea is that the clock ratios between the video @ 1080p/60Hz and the audio are off? Do they need to be synchronized?

[Mario87]

I am sorry I don't know much about HDMI, but your question is so well framed/communicated I just had to comment. The only slight idea is that the clock ratios between the video @ 1080p/60Hz and the audio are off? Do they need to be synchronized?

Thanks, however I think I might know what I need to do in order to fix it, although I am not entirely sure of the cause for it...basically I have a custom test board with headers that I can probe the signals from, so I started probing them and I noticed if I probe the MCLK or SCLK lines the audio improves, not perfect, but it improves, then I noticed if I squeeze the test header with my fingers the audio becomes perfect!

It must be the extra capacitance from my body / the probes which is making it work, but what I do not understand is why does it only need this extra capacitance on the audio lines if the video feed is at 1080p. Is the fact the FPGA is running at higher clock speeds (2.75x faster for the clock and around 11x faster for each of the 24-bit video signals) meaning that it's in turn consuming more power and not able to provide such a stable output on the audio lines?

It is a Nexys Video dev board with Artix-7 FPGA and all my signals (24-bit video, H-Sync, V-Sync, FID, H-Blank, V-Blank, I2S Audio, etc) all feed into FPGA banks 15 & 16 (due to how the dev board is designed and the need to use the FMC connector I can't really use other banks).

Is it simply too much for just those 2 banks to handle in a stable manner when having to deal with the video at higher frequencies? Would moving to a different FPGA bank resolve the issue (which I unfortunately cannot really do until I make this into a custom board and take it off the dev board).

It's strange, and I would like to figure out what is going on, but in the mean time I suspect adding some capacitors next to the inputs of the ADV7513 on MCLK, LRCLK and SCLK should make it work as I want.

[moffy]

I suspect that the extra capacitance is eliminating some extra glitches on the digital audio clocks, possible crosstalk from the 1080p@60Hz which might explain why the higher video rate is corrupting the digital audio.

[Mario87]

I suspect that the extra capacitance is eliminating some extra glitches on the digital audio clocks, possible crosstalk from the 1080p@60Hz which might explain why the higher video rate is corrupting the digital audio.

That is something that came to mind (crosstalk) as I have these headers all around the ADV7513 to make probing easy, but then I essentially have around 30-40 mini antennas and I suspect at lower frequencies they do not pick up the noise from neighboring pins so readily, but at higher frequencies, even these small antennas become good at picking up nearby interference (as in a few cm away).

What I might try (as a proof of concept) is to cover the audio pins in tape (to avoid shorting them) then place a bit of grounded copper tape or aluminium foil over the pins to see if it shields them and the audio works fine as-is.

Luckily the audio pins are along a seperate side of the ADV7513 than the other video feeds (except for V-sync, but thats only 60Hz), so should be easy to isolate the audio from an RF interference the video feed is giving off at higher frequencies.

[moffy]

I suspect that the extra capacitance is eliminating some extra glitches on the digital audio clocks, possible crosstalk from the 1080p@60Hz which might explain why the higher video rate is corrupting the digital audio.

That is something that came to mind (crosstalk) as I have these headers all around the ADV7513 to make probing easy, but then I essentially have around 30-40 mini antennas and I suspect at lower frequencies they do not pick up the noise from neighboring pins so readily, but at higher frequencies, even these small antennas become good at picking up nearby interference (as in a few cm away).

What I might try (as a proof of concept) is to cover the audio pins in tape (to avoid shorting them) then place a bit of grounded copper tape or aluminium foil over the pins to see if it shields them and the audio works fine as-is.

Luckily the audio pins are along a seperate side of the ADV7513 than the other video feeds (except for V-sync, but thats only 60Hz), so should be easy to isolate the audio from an RF interference the video feed is giving off at higher frequencies.

Sounds like a good experiment, the grounded copper tape will also introduce some capacitance, but should be a less than touching the pins.

[Mario87]

Seems like its maybe not cross talk / EMI after all, I covered the pins in kapton tape, then a layer of copper tape then used more copper tape to fix a small wire to the copper tape already in place and that wire could then be connected / disconnected to GND as I pleased.

I checked continuity and all was well, but connecting and disconnecting made no difference at all. I'll add some 100nF 0603 capacitors to LRCLK, MCLK & SCLK and see how it fares. I would have started with 22pF but I only have them in size 0805 and I am tight on space, so will need to be the 100nF 0603's.

[moffy]

I'll add some 100nF 0603 capacitors to LRCLK, MCLK & SCLK and see how it fares. I would have started with 22pF but I only have them in size 0805 and I am tight on space, so will need to be the 100nF 0603's.

Using 22pF sounds much more reasonable than 100nF if you are attaching them to the actual clock signals, the 100nF would kill the clocks. With regards to it not being EMI you have only eliminated those areas you covered with tape as the possible source. If you have the signals travelling from one board to another, that would be a possible source, as well as parallel traces on the board. Then there is the whole issue of grounding and suitable decoupling.

[Mario87]

With regards to the EMI, I did not attempt to reduce the emissions by covering areas I thought it was coming from with tape, I tried to improve immunity by covering the audio pins with tape and grounding, so I am fairly confident that it is not radiated noise from nearby headers being picked up.

However as you have said it could well be conducted emissions and that would also explain why capacitance of me touching the pins is helping, it provides a low impedance path for the high frequency elements to filter off to.

I will test with 100nF as thats all I have to work with just now, but if it does cause clock issues I can always order up some 0603 22pF caps. Really needs a sweet spot to create a low enough capacitive reactance for the high frequency noise to be filtered but also not affect the clock signals with too much capacitance in the circuit.

One reason I do believe this is likely EMI related in some form is I noticed when I run the audio wires over the headers it induces more crackling and distortion, but if I route the wires away from that area the signal quality is much better (this is with me holding the header pins for both scenarios).

[moffy]

I will test with 100nF as thats all I have to work with just now, but if it does cause clock issues I can always order up some 0603 22pF caps. Really needs a sweet spot to create a low enough capacitive reactance for the high frequency noise to be filtered but also not affect the clock signals with too much capacitance in the circuit.

Just a quick sanity check calculation, if the clock is 3.3V/2ns rise time then if you put 100nF on the clock you would need a surge current of 165A( I = Cdv/dt) to maintain the signal! Obviously the cap will look some what inductive at those frequencies and the drive can't supply such currents, but you get the idea. Whereas for 22pF you only need 36ma surges.

[Mario87]

Just a quick sanity check calculation, if the clock is 3.3V/2ns rise time then if you put 100nF on the clock you would need a surge current of 165A( I = Cdv/dt) to maintain the signal! Obviously the cap will look some what inductive at those frequencies and the drive can't supply such currents, but you get the idea. Whereas for 22pF you only need 36ma surges.

Right, so what I have managed to do is fit the 0805 22pF capacitors on the bottom of the board to LRCLK, SCLK and MCLK lines. The headers are through-hole components and are located as close to the IC as I could reasonably get, so I soldered 1 side of the caps directly to the header pin where it exits the bottom of the board and the other end of the cap to the GND plane where I just scraped off some of the solder mask to get a good solder joint.

Not had a chance to test it, but I'll do that later today and update with what happens.

[Mario87]

Right, so what I have managed to do is fit the 0805 22pF capacitors on the bottom of the board to LRCLK, SCLK and MCLK lines. The headers are through-hole components and are located as close to the IC as I could reasonably get, so I soldered 1 side of the caps directly to the header pin where it exits the bottom of the board and the other end of the cap to the GND plane where I just scraped off some of the solder mask to get a good solder joint.

Not had a chance to test it, but I'll do that later today and update with what happens.

It works perfectly!

[moffy]

Right, so what I have managed to do is fit the 0805 22pF capacitors on the bottom of the board to LRCLK, SCLK and MCLK lines. The headers are through-hole components and are located as close to the IC as I could reasonably get, so I soldered 1 side of the caps directly to the header pin where it exits the bottom of the board and the other end of the cap to the GND plane where I just scraped off some of the solder mask to get a good solder joint.

Not had a chance to test it, but I'll do that later today and update with what happens.

It works perfectly!

Brilliant!