Abusing USB-C OTG CC Pin Resistors to default to Power Sink

[weinbergerc]

The USB spec says Hosts should pull CC to 5v with a 56k resistor, and USB Devices should pull CC down to GND with a 5.1k resistor.

Edit: I've since found out about a feature called "Usb-C Dead Battery Mode", and this question can be summarized as "How do you reliably implement Usb-C Dead Battery Mode?" -- End of edit.

If you need to do USB OTG (i.e. select-ably switch Host or Device), the spec says you should use 2 Mosfets, perhaps like this:



Why the 1M pullup? My device has no battery power so by default I want it to enable the 5.1k RD1 resistor to request power when plugged into a host.

The Problem:
How can I have a predictable USB_CC voltage when in USB Host unconnected state? (RD1 disabled, RP1 enabled, USB_CC floating) In my testing when no usb device is connected and my device is powered from an external power supply (5v rail), USB_CC is at 2.1v and 2.9v are dropped across QRP1. This is not great, as ideally the transistors would drop nothing.

I came up with a simplified design that will always leave USB_CC at a well defined voltage:



but this is definitely not "to spec". There should only be a single pull-up / pull-down, and never both at the same time.

There must be a solution to this problem. How can I have a predictable voltage at USB_CC, default to Usb Power Sink, and stay within spec?

[PeteH]

You'd want a p-channel FET on the highside, pulling the gate low to turn it on.

[NiHaoMike]

Have a 5.1k resistor on the CC line going to a MOSFET to ground, then a 51k resistor from the MOSFET drain to 5V. With the MOSFET off, it will work like a 56.1k resistor to 5V. With the MOSFET on, it will work like a 5.1k resistor to ground.

[weinbergerc]

Thanks for the suggestions!

You'd want a p-channel FET on the highside, pulling the gate low to turn it on.

This seems like a good idea. I'll try this.

Have a 5.1k resistor on the CC line going to a MOSFET to ground, then a 51k resistor from the MOSFET drain to 5V. With the MOSFET off, it will work like a 56.1k resistor to 5V. With the MOSFET on, it will work like a 5.1k resistor to ground.

Something like this?



That's an interesting idea. It looks kinda weird! It does make intuitive sense that you would only need 1 mosfet to switch between 2 states.

Edit: I just tried NiHaoMike's but am not seeing the 5.1k to ground when a USB Host is connected.

Code: [Select]

Setup:
5v rail floating (as per the USB-C spec, until a host is determined 5v Usb power must remain off)
USB_RD floating (no other choice, the micro is not yet powered)
USB_CC 51k pullup (due to a USB Host being connected)

Expected Results:
        Rcc = 5.1k ohms (my device defaults to USB Device)
        Vds = 0.01v approx.

Actual Results:
Vcc = 2.02v
Icc = 0.053mA
Rcc = 38k ohms
Vds = 1.71v

[NiHaoMike]

If you need it to reliably "cold start", you'll have to use a MOSFET with a sufficiently low threshold voltage.

[weinbergerc]

That makes sense, but given that 5.1k / (5.1k+56k) * 5v = 0.417v, do I have enough voltage to turn on any transistor? LCSC shows 450mv as the lowest Vgs(ths) available right now.

Or do I just have the wrong approach entirely? Maybe I should leave the 5.1k connected to ground and enable a current source instead of the Rp pull-up.

 The 5v rail is not available until *after* I present the 5.1k to GND. I just have the USB-CC voltage to work with.

[weinbergerc]

Here is a implementation I found: https://community.infineon.com/t5/Knowledge-Base-Articles/DEAD-BATTERY-CHARGING-IMPLEMENTATION-IN-CCG1-SOLUTIONS-KBA97273/ta-p/259059

They use a BSD840N, which has a pretty low Vgs(th) of 300mV minimum.

[NiHaoMike]

Another possible solution is a P channel JFET, which defaults to on and is turned off by applying a positive voltage to the gate.

[weinbergerc]

Buying some P-type JFETs right now! I'll try it!

Really really appreciate your help. I was getting stressed about how on earth I was going to fix this.

[weinbergerc]

Looking at some JFET characteristics curves, it seems like 0.42v Vds will not be enough to be "fully on".

Edit: nvm I misunderstood JFETS. It will have near 0 resistance at Vgs=0 regardless of low Vds

I'll still be well within in the ohmic region with a large resistance?

If so, that seems like a no-go, unless the resistance is very stable and knowable in advance to account for it.