Max current density for 35 µm Cu FR4 PCB?

[voja]

Is there any standard (or, at least, recommendation) for max current in A/mm (track width) for 35 µm thick Cu track?
Also, which is the minimum space between PCB tracks for 220VAC? I've heard that it is 5mm for regular applications, and 8mm for medical or life saving devices, is it true? Some PCB connectors are listed as 220VAC, but they have even smaller pitch, which contradicts this.

[Falcon69]

this may help you.

http://circuitcalculator.com/wordpress/2006/01/31/pcb-trace-width-calculator/

[digsys]

I use a reference chart as a guide, based on actual test results I carry out on supplied batches.
IF I really need to verify the specs, I place 5-10cm tracks along the PCB, full/80% mask etc, somewhere unobtrusive.
I can then do a RW test on each PCB batch.

[T3sl4co1l]

The upper limit to reliable operation, physically speaking, is due to electromigration.  Which apparently is in the 10^7 A/cm^2 range.  Whereas most wires and traces are in the 10^3 A/cm^2 range.  So, you have about an 80dB dynamic range between burning out traces due to overheating (in the 100us to 100s time scales), until peak currents (ESD and other surges?) even begin to affect the conductor physically.

Current density isn't really a thing, when it comes to heating, but you can determine an upper limit.

Suppose the board is covered in a uniform layer of copper, which is carrying a uniform current.  The copper plating has known resistance, and the board has a certain dissipation factor (typically around 8.3mW / (in^2 K)) due to convection on the surface (top and bottom, separately), and you define a fixed temperature rise for the board.

If you plug all these in, you get:
Missing variable: resistivity of copper ~ 17nOhm.m.  Let's say 20, since it has some tempco and as-plated won't exactly be annealed either.

https://www.google.com/search?q=sqrt%281%2F%281+in+*+20+nanoohm+meter%29+*+%280.0083+watt%2Fin%5E2%2Fkelvin%29+*+20+kelvin%29+in+A%2Fcm%5E2

For a 20C (= 20K) temp rise.

(I wrote this before, just rearranged for current density.  Ref: http://www.dutchforce.com/~eforum/index.php?showtopic=43392 )

If the thermal conductivity of the PCB is good (for FR-4, not really..), you can concentrate all the current on one side, but get dissipation from two sides; as a result, the current density limit goes up by up to 40%.  It goes up further if there is a ratio of copper area to board area (i.e., you have a bunch of individual traces carrying current, separated by blank board area that's insulating around the traces but still able to dissipate heat).  Although not by too much, because again -- limited by board conductivity.  But if the board conductivity is good (say, an internal copper plane, spreading heat), it's even better still.

So current density for individual traces can be maybe 200-300% higher.

The IPC-2152 calculation (see http://www.smps.us/pcb-calculator.html ) takes these factors into account.  The two-sided PCB case is very close to the above figures (yay for consistency!), which is consistent with the old IPC-2221 figure.  The values for internal planes and stuff are better still.

Tim

[tszaboo]

Depends on your acceptable temperature rise, number of layers, layers stackup, parallel conductors, PCB temperature, frequency of the current, and ariflow.

So, I guess 5 potatoes/microHenry.
http://www.saturnpcb.com/pcb_toolkit.htm

[free_electron]

in terms of isolation you need to differentiate between creepage and clearance.
you need to know the classification of your board. ( environment)

http://www.creepage.com/

[voja]

Thaks to everyone!
Very useful informaton

[Howardlong]

Completely coincidentally, yesterday I spent some time making some tables up in a spreadsheet to laminate so I don't have to keep jumping to a website to do a calculation for PCB trace widths.

It covers current handling for 10 deg C raise (internal and external layers), microstrip for 50 and 75 ohm and a simple mil<->mm conversion table.

I attach the PDFs for laminating and the original spreadsheet (zipped).

[37electrons]

With regards to max current via PCB tracks - Saturn PCB Toolkit is your friend (NANDBlog provided the link above). This app uses formulas from IPC standards for calculations so they're conservative enough to rely upon.

Regarding clearances, 5mm sounds OK if 220Vac is used. In addition to two documents that free_electron attached, I'd also recommend another nice tutorial here ftp://ftp.ni.com/pub/devzone/tut/safety_isolation_protects.pdf

Note however, that all these documents (including mine) are a bit outdated (2004-2005) and they may refer to safety standards which are obsolete now. Since 2009 IEC/EN 60950-1 removed PCBs from the table 2N (which shows creepage vs working voltage values). PCBs are not treated in any special way now and should follow general rules.

See the table from the currently valid IEC 60950-1 standard attached. For clean indoor environments you should take pollution degree = 2 (1 is only for internal layers of your board or for PCBs with extra conformal coating. Solder mask is not considered as a protection against pollution now). Material group depends on PCB CTI (http://en.wikipedia.org/wiki/Comparative_Tracking_Index) value and typically (for most common laminates) is IIIa. Values in the table are for basic insulation. Double them for reinforced insulation. So it's at least 5mm for 250Vrms (for indoor use & external PCB layers). The more - the better, of course. Play safe with mains.