I got the board and soldered the first channel:
You were right, I can just connect VRB to GND and it converts down to 0 output reading. For VRT I used the 4 V reference.
A first test with 1 MHz square wave had some overshooting. I added a 1 pF capacitor for C3, no capacitor for C1, and it looked like this:
I guess the potentiometer RV2 adds some more capacitance, because I could even lower it to 0.5 pF. Then it starts to wiggle a bit, but even better edges:
The FPGA is sampling it with 25 MHz and I read it over the serial port with 1 Mbaud with
this Python script, which also displays the nice oscilloscope diagrams and updates it live, with about 2 seconds per frame.
Next will be soldering the other 3 channels. Then I will finish the FPGA programming, because at the moment I'm using just the internal block RAM, but I plan to use the 1 GB DDR3 RAM. I hope I can save all the data at this bandwidth. Maybe I need to add a FIFO for saving it without gaps, in case the DDR RAM decides to do a refresh etc.
Later I can use the ARM on the Cyclone 5 and Linux to transfer the data over ethernet. But this might be some work to access the DDR RAM from both, the ARM and the FPGA part of the Cyclone 5, and Linux driver development etc. But shouldn't be too much work.